Thread (77 messages) flat view 77 messages, 11 authors, 2012-07-06
STALE5145d

[PATCH 16/16] ARM: imx: enable SPARSE_IRQ for imx platform

From: haojian.zhuang@gmail.com (Haojian Zhuang)
Date: 2012-06-14 07:40:09

On Thu, Jun 14, 2012 at 1:59 PM, Shawn Guo [off-list ref] wrote:
As all irqchips on imx have been changed to allocate their irq_descs,
and all unneeded mach/irqs.h inclusions on imx have been cleaned up,
now it's time to select SPARSE_IRQ for imx/mxc.

The SPARSE_IRQ support forces irqs allocation starting from 16. ?All
those static irq number definition for SoCs need to shift 16 to keep
non-DT boot works.
Do we really need to shift 16 to keep non-DT boot works?

I think that we can allocate "new irq numbers - NR_IRQS_LEGACY" in interrupt
controller in DT mode. And we needn't shift NR_IRQS_LEGACY in non-DT mode,
since irq numbers are already specified in .nr_irqs of machine description.

Maybe you can reference code in arch/arm/mach-mm/irq.c &
arch/arm/mach-mm/brownstone.c.

Regards
Haojian
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