* Mitch Bradley wrote:

On 6/12/2012 9:46 AM, Stephen Warren wrote:

quoted

On 06/12/2012 01:10 PM, Mitch Bradley wrote:

quoted

On 6/12/2012 7:20 AM, Thierry Reding wrote:

...

quoted

quoted

I came up with the following alternative:

pci {
	compatible = "nvidia,tegra20-pcie";
	reg =<0x80003000 0x00000800   /* PADS registers */
	       0x80003800 0x00000200   /* AFI registers */
	       0x80004000 0x00100000   /* configuration space */
	       0x80104000 0x00100000   /* extended configuration space */
	       0x80400000 0x00010000   /* downstream I/O */
	       0x90000000 0x10000000   /* non-prefetchable memory */
	       0xa0000000 0x10000000>; /* prefetchable memory */
	interrupts =<0 98 0x04   /* controller interrupt */
	              0 99 0x04>; /* MSI interrupt */
	status = "disabled";

	ranges =<0x80000000 0x80000000 0x00002000   /* 2 root ports */
		  0x80004000 0x80004000 0x00100000   /* configuration space */
		  0x80104000 0x80104000 0x00100000   /* extended configuration space */
		  0x80400000 0x80400000 0x00010000   /* downstream I/O */
		  0x90000000 0x90000000 0x10000000   /* non-prefetchable memory */
		  0xa0000000 0xa0000000 0x10000000>; /* prefetchable memory */

	#address-cells =<1>;
	#size-cells =<1>;

	port at 80000000 {
		reg =<0x80000000 0x00001000>;
		status = "disabled";
	};

	port at 80001000 {
		reg =<0x80001000 0x00001000>;
		status = "disabled";
	};
};

The "ranges" property can probably be cleaned up a bit, but the most
interesting part is the port@ children, which can simply be enabled in board
DTS files by setting the status property to "okay". I find that somewhat more
intuitive to the variant with an "enable-ports" property.

What do you think of this?

The problem is that children of a PCI-ish bus have specific expectations
about the parent address format - the standard 3-address-cell PCI
addressing.  So making a PCI bus node - even if it is PCIe - with 1
address cell is a problem.

Couldn't you put the #address-cells=<3>  underneath each port node, and
put any PCIe devices there rather than under the main PCIe controller
node? I'm not sure how the interrupt mapping table etc. would work in
that case, but that seems to solve the addressing issue.

Yes, that would work just fine, and in fact would be preferable, if
a "root port" is essentially an independent PCI bus.  The parent of
those root ports should not be named "pci", though, as it is not in
itself a PCI bus.  It could be called "pcis".

Yes, on Tegra each of the ports provides a separate PCI bus. How about naming
the parent "pcie-controller"? IMO that reflects the nature of the device
better, whereas "pcis" would seem more like a "virtual" node for collecting
similar children.

Thierry
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