Le mercredi 30 mai 2012 18:08:38 Mark Brown a ?crit :

quoted

On Tue, May 29, 2012 at 11:06:29AM +0200, Philippe R?tornaz wrote:

quoted

The MC13xxx PMIC is mainly used on i.Mx SoC. On thoses SoC the SPI
hardware will deassert CS line as soon as the SPI FIFO is empty.
The MC13xxx hardware is very sensitive to CS line change as it
corrupts the transfert if CS is deasserted in the middle of a register
read or write.
It is not possible to use the CS line as a GPIO on some SoC, so we
need to workaround this by implementing a single SPI transfer to
access the PMIC.

Reviwed-by: Mark Brown [off-list ref]

though it's really sad this can't be done in the SPI controller where
the bug is.  You should also set use_single_rw in the regmap_config,
though this is less critical as currently the core won't automatically
generate any bulk I/O.

I already put it in struct regmap_config, should I put it elsewhere ? 

@@ -54,6 +54,67 @@ static struct regmap_config mc13xxx_regmap_spi_config = {
        .max_register = MC13XXX_NUMREGS,
 
        .cache_type = REGCACHE_NONE,
+       .use_single_rw = 1,
+};

BTW, who will merge this patchset ?