Hi Will

On 05/11/2012 07:25 AM, Will Deacon wrote:

On Thu, May 10, 2012 at 07:55:01PM +0100, Jon Hunter wrote:

quoted

Hi Will,

Hi Jon,

quoted

For my testing I have just been reading the PM_EMU_PWRSTST register which shows the power state of the EMU power domain. It should read 3 when the power domain is ON and 0 when it is off. I did something like the following (dumping all EMU clock and power domain registers).

I figured I may as well take perf for a spin and see how I got on. The good
news is that the hwmod bits all seem to work as before and the correct IRQs
are requested:

root at florentine-pogen:~# cat /proc/interrupts
           CPU0       CPU1
 29:      44527      17916       GIC  twd
 33:          0          0       GIC  arm-pmu
 34:          0          0       GIC  arm-pmu

But, unfortunately, as you can see from the above, I just can't persuade them
to fire. The PMU counters do tick, but they happily increment through zero
without us realising. I retested with my perf/omap4 branch to make sure my
board is ok, and the irqs do fire there.

Any ideas?

Do you disable OMAP2/3 support in the kernel config, so that CPU_HAS_PMU
is enabled?

Cheers
Jon