What if a module needs two clocks and you drive the reset on both of the
clocks ? What would happen ?

Only 'leave clocks' have this reset method and a module can only have 1 of
them.

quoted

but then we would have the keep a list of IDs (1 per module) which the drivers
can use to call some tegra reset function which would in the end use registers
in the same memory area to cause a reset. (the registers controlling
modulereset are interleaved with those controlling the enable/disable of the
main moduleclock and bitpositions are identical)

Well, under a generic device-level API, you could just call an internal
clk_reset() function because you know which clocks feed into which
devices anyway. It could look something like:

on Tegra:

device_reset(dev)
	-> dev_pm_domain->reset()
		-> tegra_periph_reset()

These methods are also needed internally by the powergating code.

on OMAP:

device_reset(dev)
	-> dev_pm_domain->reset()
		-> omap_hwmod_reset()


btw:

tegra_periph_reset(....)
{
	tegra_periph_reset_assert(...);
	udelay(2);
	tegra_periph_reset_deassert(...);
}

which uses the clockframework currently.

Cheers,

Peter.