On 05/07/2012 05:36 AM, Hiroshi Doyu wrote:
...

Tegra AHB Bus conforms to the AMBA Specification (Rev 2.0) Advanced
High-performance Bus (AHB) architecture.

The AHB Arbiter controls AHB bus master arbitration. This effectively
forms a second level of arbitration for access to the memory
controller through the AHB Slave Memory device. The AHB pre-fetch
logic can be configured to enhance performance for devices doing
sequential access. Each AHB master is assigned to either the high or
low priority bin. Both Tegra20/30 have this AHB bus.

I've applied this (minus the Change-Id line) and the other two patches
to Tegra's for-next branch. I'll let it sit there for a day or two
before sending a pull request into arm-soc for 3.5; hopefully it's not
too late for that.