[PATCH v7 08/14] arm/tegra: generalize L2 cache initialization
From: Peter De Schrijver <hidden>
Date: 2011-12-14 15:08:16
Also in:
linux-devicetree, linux-tegra, lkml
Subsystem:
arm port, the rest · Maintainers:
Russell King, Linus Torvalds
Generalize L2 cache initialization and discover L2 cache associativity at runtime. Signed-off-by: Peter De Schrijver <redacted> --- arch/arm/mach-tegra/common.c | 15 ++++++++++----- 1 files changed, 10 insertions(+), 5 deletions(-)
diff --git a/arch/arm/mach-tegra/common.c b/arch/arm/mach-tegra/common.c
index 8da1847..554f18f 100644
--- a/arch/arm/mach-tegra/common.c
+++ b/arch/arm/mach-tegra/common.c@@ -73,15 +73,20 @@ static __initdata struct tegra_clk_init_table tegra20_clk_init_table[] = { }; #endif -static void __init tegra_init_cache(void) +static void __init tegra_init_cache(u32 tag_latency, u32 data_latency) { #ifdef CONFIG_CACHE_L2X0 void __iomem *p = IO_ADDRESS(TEGRA_ARM_PERIF_BASE) + 0x3000; + u32 aux_ctrl, cache_type; - writel_relaxed(0x331, p + L2X0_TAG_LATENCY_CTRL); - writel_relaxed(0x441, p + L2X0_DATA_LATENCY_CTRL); + writel_relaxed(tag_latency, p + L2X0_TAG_LATENCY_CTRL); + writel_relaxed(data_latency, p + L2X0_DATA_LATENCY_CTRL); - l2x0_init(p, 0x6C080001, 0x8200c3fe); + cache_type = readl(p + L2X0_CACHE_TYPE); + aux_ctrl = (cache_type & 0x700) << (17-8); + aux_ctrl |= 0x6C000001; + + l2x0_init(p, aux_ctrl, 0x8200c3fe); #endif }
@@ -92,6 +97,6 @@ void __init tegra20_init_early(void) tegra_init_fuse(); tegra2_init_clocks(); tegra_clk_init_from_table(tegra20_clk_init_table); - tegra_init_cache(); + tegra_init_cache(0x331, 0x441); } #endif
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1.7.7.rc0.72.g4b5ea.dirty