Hi Alan,

Thanks for your comment.

On Tue, Aug 30, 2011 at 12:33 AM, Alan Stern [off-list ref] wrote:

Nevertheless, it remains true that you want to add a memory barrier
instruction simply in order to speed up a cache writeback, not to force
any sort of ordering. ?This needs to be explained carefully in the code
(not just in the patch description!) and it needs to be done in a way
that won't affect other architectures.

OK, will do it.

Also, as you mentioned before, you may want to do the same thing in
qh_link_async() just after the

? ? ? ?head->hw->hw_next = dma;

line. ?Delays in flushing that write would also slow down performance.

Will do it too.


thanks,
--
Ming Lei