[PATCH 10/10] ARM: perf: add mode exclusion for Cortex-A15 PMU

On Thu, Aug 25, 2011 at 04:09:13AM +0100, Ashwin Chaugule wrote:

Hey Will,

Hi Ashwin,

quoted

From: Will Deacon <redacted>

The Cortex-A15 PMU implements the PMUv2 specification and therefore
has support for some mode exclusion.

This patch adds support for excluding user, kernel and hypervisor counts
from a given event.

Signed-off-by: Will Deacon <redacted>
---

--8<---

quoted

+
+/*
+ * Event filters for PMUv2
+ */
+#define        ARMV7_EXCLUDE_PL1       (1 << 31)
+#define        ARMV7_EXCLUDE_USER      (1 << 30)
+#define        ARMV7_INCLUDE_HYP       (1 << 27)
+

This mode exclusion stuff is confusing me.

I'm not surprised, the wording is pretty hard to follow in the
documentation.

For exclude user mode, shouldn't PMXEVTYPER[PL1,U] = 0b11

No - this is a reserved encoding and results in the counters stopping for
*all* modes!

With this patch the counters will spin with secure mode activity as well,
if exclude user mode is selected ?

Yes, but they won't tick for either secure or non-secure user-mode, which is
what we want. Note that secure software can stop the counters ticking by
messing with the SDER.

/me goes to bother the h/w guys.

Bah, they deserve it :)

Will