[PATCH kernel-3.0] arm:cache-l2x0: Fix L2 Cache size calculation.

On Fri, Aug 12, 2011 at 10:45:27AM +0100, Srinivas KANDAGATLA wrote:

From: Srinivas Kandagatla <redacted>

This patch fixes L2 Cache size calculations for L2C-210, L2C-310 and
PL310, by changing the L2X0_AUX_CTRL_WAY_SIZE_MASK from 2 bits to 3
bits.

The Auxiliary Control Register for L2C-210, L2C-310 and PL310 has 3bits
[19:17] for Way size, however the existing code only uses 2 bits to
get this value. This results in incorrect cachesize calculations.

I should say this bug does not result in issue but, its just prints
incorrect values.

It also results in performing operations on the whole cache when we
erroneously decide that the range is big enough (due to l2x0_size being
too small).

Signed-off-by: Srinivas Kandagatla <redacted>

Acked-by: Will Deacon <redacted>

Please can you CC stable on this too?

Will