On Wed, 10 Aug 2011 15:51:19 +0530
Thomas Abraham [off-list ref] wrote:

s3c64xx and later SoC's include the interrupt mask and pending
registers in the uart controller, unlike the s3c24xx SoC's which have
these registers in the interrupt controller. When the mask and
pending registers are part of the uart controller, a unified
interrupt handler can handle the tx/rx interrupt. With this, the
static reservation of interrupt numbers for the uart tx/rx/err
interrupts in the linux irq space is not required and simplifies
adding device tree support.

Really only hardware changes so for the tty touching aspect of it

Acked-by: Alan Cox <redacted>