[PATCH v4 2/5] mmc: support sdhci-pxav2.c
flat view
STALE5595d
From: Philip Rakity <hidden>
Date: 2011-06-13 21:35:26
Also in:
linux-mmc
Revision v4 of 4 in this series.
On Jun 8, 2011, at 2:41 AM, Zhangfei Gao wrote:
SDHCI driver for PXAV2 SoCs, such as pxa910, the driver based on sdhci-pltfm to handle resource etc. Signed-off-by: Zhangfei Gao <redacted> Signed-off-by: Jun Nie <redacted> Signed-off-by: Qiming Wu <redacted> ---
quoted hunk ↗ jump to hunk
+++ b/drivers/mmc/host/sdhci-pxav2.c + +#define SD_FIFO_PARAM 0xe0 +#define DIS_PAD_SD_CLK_GATE 0x0400 /* Turn on/off Dynamic SD Clock Gating */ +#define CLK_GATE_ON 0x0200 /* Disable/enable Clock Gate */ +#define CLK_GATE_CTL 0x0100 /* Clock Gate Control */ +#define CLK_GATE_SETTING_BITS (DIS_PAD_SD_CLK_GATE | \ + CLK_GATE_ON | CLK_GATE_CTL) + +#define SD_CLOCK_BURST_SIZE_SETUP 0xe6 +#define SDCLK_SEL_SHIFT 8 +#define SDCLK_SEL_MASK 0x3 +#define SDCLK_DELAY_SHIFT 10 +#define SDCLK_DELAY_MASK 0x3c + +#define SD_CE_ATA_2 0xea +#define MMC_CARD 0x1000 +#define MMC_WIDTH 0x0100 + +static void pxav2_set_private_registers(struct sdhci_host *host, u8 mask) +{ + struct platform_device *pdev = to_platform_device(mmc_dev(host->mmc)); + struct sdhci_pxa_platdata *pdata = pdev->dev.platform_data; + + if (mask == SDHCI_RESET_ALL) { + u16 tmp = 0; + + /* + * tune timing of read data/command when crc error happen + * no performance impact + */ + if (pdata->clk_delay_sel == 1) { + tmp = readw(host->ioaddr + SD_CLOCK_BURST_SIZE_SETUP); + + tmp &= ~(SDCLK_DELAY_MASK << SDCLK_DELAY_SHIFT); + tmp |= (pdata->clk_delay_cycles & SDCLK_DELAY_MASK) + << SDCLK_DELAY_SHIFT; + tmp &= ~(SDCLK_SEL_MASK << SDCLK_SEL_SHIFT); + tmp |= (1 & SDCLK_SEL_MASK) << SDCLK_SEL_SHIFT; + + writew(tmp, host->ioaddr + SD_CLOCK_BURST_SIZE_SETUP); + }
There are 3 possible value for clk_delay_sel.
0 == do not use clk_delay_cycles
1 == use programmed clk_delay_cycles value (the code above)
all other values use the sd_clk which was used to drive the output
The code about only handles 2 of the 3 cases
suggest
(if (pdata->clk_delay_sel) {quoted hunk ↗ jump to hunk
+ if (pdata->clk_delay_sel == 1) { + tmp = readw(host->ioaddr + SD_CLOCK_BURST_SIZE_SETUP); + + tmp &= ~(SDCLK_DELAY_MASK << SDCLK_DELAY_SHIFT); + tmp |= (pdata->clk_delay_cycles & SDCLK_DELAY_MASK) + << SDCLK_DELAY_SHIFT; + tmp &= ~(SDCLK_SEL_MASK << SDCLK_SEL_SHIFT); + tmp |= 1 << SDCLK_SEL_SHIFT; + + writew(tmp, host->ioaddr + SD_CLOCK_BURST_SIZE_SETUP); + } else {
quoted hunk ↗ jump to hunk
+ tmp = readw(host->ioaddr + SD_CLOCK_BURST_SIZE_SETUP); + tmp &= ~(SDCLK_SEL_MASK << SDCLK_SEL_SHIFT); + tmp |= 2 << SDCLK_SEL_SHIFT; + writew(tmp, host->ioaddr + SD_CLOCK_BURST_SIZE_SETUP);
}
}
Philip and Mark