On Wed, 2011-03-30 at 19:46 +0300, Viktor Rosendahl wrote:

On 03/30/2011 06:52 PM, ext Tixy wrote:

quoted

If we start littering the code with all these extra checks we risk
introducing bugs and making the code more difficult to maintain.

In my opinion we should not add any extra code to handle instructions
combinations that the ARM ARM says are UNPREDICTABLE, or have fields
which are SBZ/SBO. The toolchain shouldn't ever generate these bad
instructions in which case the extra kprobes code is redundant.

I see your point. I guess we can decide to not care about those 
unpredictable cases, unless someone can come up with some decoding & 
checking code that covers all the cases and is easy to understand and 
maintain.

I came to my conclusion because I was trying to verify the PC writeback
fix by looking at the ARM ARM and checking that all of the 20 or so
encodings [1] of LDR/STR instructions handled by the routine actually
had the prefix and writeback bits we were testing. I think they did, but
it was very tedious, and I thought I could easily miss something and
then we might end up introducing a new bug.

If ARM were still a RISC processor then things would be a lot easier ;-)

-- 
Tixy

[1] In ARM ARM, See
    Table A5-15 Single data transfer instructions
    Table A5-10 Extra load/store instructions
    Table A5-11 Extra load/store instructions (unprivileged)