[PATCH 1/2] ARM: perf: reset counters on all CPUs during initialisation

Hi Jean,

On Wed, Mar 16, 2011 at 4:38 PM, Will Deacon [off-list ref] wrote:

quoted

ARMv7 dictates that the interrupt-enable and count-enable registers for
each PMU counter are UNKNOWN following core reset.

Great! Is this development driven by actual issues or by precaution?

Just precautionary, but it's also a precursor to some power management
work in ARM which might leave the registers in a funny state when they
come out of a low-power state. This code at least gives them an entry
hook for dealing with that.
 

quoted

This patch adds an arch_initcall to the ARMv7 perf events backend which
disables the counters on each CPU prior to setting the Enable bit in the
PMCR.

Also the function rename is a good thing.

Yup.

quoted

Cc: Jean Pihet <redacted>
Signed-off-by: Will Deacon <redacted>

Acked-by: Jean Pihet <redacted>

Thanks for the Ack,

Will