[RFC] ARM: Cortex-A9: Enable dynamic clock gating

On Wed, 2011-02-23 at 03:55 +0000, Todd Poynor wrote:

Enable dynamic high level clock gating for Cortex-A9 CPUs, as
described in 2.3.3 "Dynamic high level clock gating" of the
Cortex-A9 TRM.  This may cut the clock of the integer core,
system control block, and Data Engine in certain conditions.

Add ARM errata 720791 to avoid corrupting the Jazelle
instruction stream on earlier Cortex-A9 revisions.

Signed-off-by: Todd Poynor <redacted>
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Can anyone advise whether this feature should be selectively
enabled (or otherwise modified) due to secured register access,
introduced latencies observed, etc.?

This has been tested on a few Tegra 2 boards without problems
observed thus far, and some preliminary testing indicates it
may result in fairly significant power savings.  Any additional
testing greatly appreciated.

I haven't done any benchmarks on this, so can't comment on this.

My view is that something like the boot monitor/firmware should set this
up, though that's not always the case. On some OMAP boards Linux runs in
non-secure mode and it will fault when trying to set this bit.

-- 
Catalin