Thread (6 messages) 6 messages, 2 authors, 2011-02-11
STALE5599d

[PATCH] mmci: make sure DMA transfers wait for FIFO drain

From: Linus Walleij <hidden>
Date: 2011-02-01 14:11:00

2011/2/1 Russell King - ARM Linux [off-list ref]:
On Mon, Jan 31, 2011 at 10:39:40PM +0100, Linus Walleij wrote:
quoted
The DMA mode also needs to wait until the FIFO is drained before
enabling the MCI_DATAEND IRQ.
Hmm. ?This will cause attempted DMA usage on ARM MMCI primecells to get
stuck as we'll wait for the never-delivered callback.

With the code I have in place, you'll notice I have:

? ? ? ?/* Wait up to 1ms for the DMA to complete */
? ? ? ?for (i = 0; ; i++) {
? ? ? ? ? ? ? ?status = readl(host->base + MMCISTATUS);
? ? ? ? ? ? ? ?if (!(status & MCI_RXDATAAVLBLMASK) || i >= 100)
? ? ? ? ? ? ? ? ? ? ? ?break;
? ? ? ? ? ? ? ?udelay(10);
? ? ? ?}

This waits for the DMA controller to read the last data out of the FIFO
before allowing the request to complete. ?As it has a timeout, it is
able to detect ARMs broken DMA setup on their MMCI/DMAC, and disable DMA
support for this primecell rather than getting stuck.

This may be sufficient without using the DMA callbacks.
Seems like so. When I try it with the last patch to use the FIFO
for small xfers it works nicely.

So we'll drop this approach for now.

Linus Walleij
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