Hello Santosh,
On Fri, 28 Jan 2011, Santosh Shilimkar wrote:
On OMAP4, one can explicitly program INACTIVE as the power state of
the logic area inside the power domain. Techincally PD state programmed
to ON and if all the clock domains within the PD are idled, is equivalent
tp PD programmed to INACTIVE and all the clock domains within the PD are
idled. There won't be any power difference in above two.
Since the CPUIDLE C-states explicitly make use of INACTIVE as a PD
targeted state and also there is some additional latancy involved
with PD INACTIVE vs PD ON, it's better to support it as an explcit
PD state.
This patch adds the support to allow explicit PD INACTIVE
programming if supported.
What does the hardware do when the powerdomain is programmed to INACTIVE?
Does it actually force the clockdomains idle?
- Paul