On Wed, Jan 19, 2011 at 04:52:46PM +0800, Russell King - ARM Linux wrote:

On Wed, Jan 19, 2011 at 11:33:09AM +0530, Shiraz Hashim wrote:

quoted

Hello Russell,

On Wed, Jan 19, 2011 at 12:06:55AM +0800, Russell King - ARM Linux wrote:

quoted

Do you really need to sync back to L2, or will a dsb() do here - and
as the spinlock code uses dsb() + sev() together, would it make sense
to combine the two?  (dsb() is required to ensure all previous writes
are visible prior to the sev() executing.)

Presently L2 cache is initialized after we bootup secondary CPU but
one can have the possibility of initializing L2 earlier also.
So this would be safer.

It shouldn't make any difference as we explicitly flush the required
data for the secondary while it is incoherent out of L2 into RAM -
that being secondary_data and pen_release.

OK, but sev must follow after the SPEAR13XX_SYS_LOCATION has been
updated as secondary CPU boot code is in wfe and expects the location
to be updated when it is woken.

-- 
regards
Shiraz