On Fri, Jan 21, 2011 at 08:57:42AM -0800, Brent DeGraaf wrote:

Russell,

I just had a chat with Daniel and I think I understand what you're doing
now.  The reason for the original change was to ensure there was a barrier
(dmb minimum) between population of the nc box structure and the command
port write to the datamover.

With the original code structure, the dsb for the cache management is
happening too early to benefit the nc writes.

That DSB has precisely *nothing* to do with making sure that anything but
the cache operations which the DMA API performed are complete by the time
the API returns.

Since dsbs are costly operations, I elected to call the other api, then do
the cache management with its barrier after everything was populated.

Since the nc box and the command port writes are not using writel to do
their assignment (unless I'm missing some change here),

You must not use writel on anything but ioremapped memory.  So that's
correct.

Writing to the device registers though should be using a memory accessor
like writel.  That contains the necessary barrier to ensure that any
previous writes to memory will be ordered with respect to device writes.

As you seem to already be using writel, you have all the necessary barriers
in place provided by architecture code.