On Mon, Jun 21, 2010 at 10:20:29AM +0100, Catalin Marinas wrote:
ARMv7 processors like Cortex-A9 broadcast the cache maintenance
operations in hardware. This patch allows the
flush_dcache_page/update_mmu_cache pair to work in lazy flushing mode
similar to the UP case.
No. We know that this trick can't be used on SMP, because update_mmu_cache
is called after the PTE has been established and the page has become
visible to other CPUs in the system.
So this optimization must remain disabled on SMP for correctness.