[patch 2/4] [ARM] mmp: support marvell ARMADA610

On Mon, Jan 4, 2010 at 5:27 AM, Russell King - ARM Linux
[off-list ref] wrote:

On Mon, Jan 04, 2010 at 05:15:22AM -0500, Haojian Zhuang wrote:

quoted

On Sun, Jan 3, 2010 at 11:27 PM, Eric Miao [off-list ref] wrote:

quoted

? ? ? ?.macro ?get_irqnr_preamble, base, tmp
? ? ? ?mrc ? ? p15, 0, \tmp, c0, c0, 0 ? ? ? ? @ CPUID
? ? ? ?mov ? ? \tmp, \tmp, lsr #4
? ? ? ?and ? ? \tmp, \tmp, #0xff0
? ? ? ?cmp ? ? \tmp, #0x580

I have some concern on compressing 12-bit to 8-bit. Maybe it would not
fit chips in future.

The spec for immediate constants is: any 32-bit constant, which may be
rotated by an even number of shift places to form a single 8-bit
constant.

So, 0x0ff00000 is legal (0xff rotated left 20). ?0x07f800000 is not (0xff
rotated left 19). ?0xfc000003 is legal (0xff rotated left 26).

This comes directly from the instruction coding, which is an 8-bit
constant plus a 4-bit shift.

quoted

quoted

? ? ? ?ldrne ? \base, =ICU_AP_IRQ_SEL_INT_NUM
? ? ? ?ldreq ? \base, =ICU_MMP2_PJ4_IRQ_SEL
? ? ? ?.endm

? ? ? ?.macro ?arch_ret_to_user, tmp1, tmp2
? ? ? ?.endm

? ? ? ?.macro ?get_irqnr_and_base, irqnr, irqstat, base, tmp
? ? ? ?ldr ? ? \tmp, [\base] ? ? ? ? ? @ AP INT SEL register
? ? ? ?and ? ? \irqnr, \tmp, #0x3f
? ? ? ?tst ? ? \tmp, #(1 << 6)
? ? ? ?.endm

It's wrong at here. Whatever we need to access ICU register in
get_irqnr_and_base.

? ? ? ? .macro irq_handler
? ? ? ? get_irqnr_preamble ?r5, lr
1: ? ? get_irqnr_and_base ?r0, r6, r5, lr
? ? ? ? ...
? ? ? ? bne ?asm_do_IRQ

If we just keep accessing ICU register in get_irqnr_preamble, we'll
find lr register used in asm_do_IRQ. When the loop came back to
get_irqnr_and_base(), we'll meet unpredicated value.

I don't see what you're getting at - Eric only uses the 'tmp' register
as a local temporary in each macro. ?It's entirely local to that
macro, and each macro doesn't care what value it had previously.

The first thing that get_irqnr_and_base does is overwrite 'lr' with
the value from the INT SEL register.

OK. Update the patches.
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