Thread (6 messages) 6 messages, 2 authors, 2009-11-10
DORMANTno replies

[PATCH 3/6] pxa: fix pxa168 lcd controller vsync/hsync timing error

From: Jun Nie <hidden>
Date: 2009-11-10 05:18:42
Also in: linux-fbdev

2009/11/9 Eric Miao [off-list ref]:
quoted
quoted
Could you please help double check this? My understanding is
FB_SYNC_VERT_HIGH_ACT means it's a positive pulse covering all the
valid HSYNCs, and a rising edge of VSYNC means a start of the frame.

However, CFG_INV_VSYNC is '1' means the opposite.
My understanding is that high active means high level trigger new
frame/line. Below page support my point if it is not wrong.

http://www.arcadecollecting.com/info/Sync_fixing.txt
Tried to find the specific diagram in the spec on what CFG_INV_* means
but failed, can you help verified this with an oscilloscope and let know
the result? This is a fix then, and I'd like it to get into .32, sorry for late
reply.
Hi, Eric
If do not set CFG_INV_VSYNC and CFG_INV_HSYNC bits, controller output
is as below in oscilloscope.

                  ||               ||                ||
.._________||_________||_________||____... HSYNC (active high)

                                                    _____
                                                     |     |
.._____________________________|     |_... VSYNC (active high)

So I should mark HSYNC_HIGH and VSYNC_HIGH in platform code and keep
driver code as  below original code.
       x |= (info->var.sync & FB_SYNC_VERT_HIGH_ACT) ? 0 : 0x00000008;
       x |= (info->var.sync & FB_SYNC_HOR_HIGH_ACT) ? 0 : 0x00000004;

Thanks!

Jun
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