On Sat, 2009-09-26 at 23:58 +0200, Linus Walleij wrote:

2009/9/25 Linus Walleij [off-list ref]:

quoted

2009/9/25 Peter Chen [off-list ref]:

quoted

quoted

1. After MMU open, the code running at ITCM can't see physical address for
register.

2. After MMU open, the code can't run at physical addressed ITCM.

Could this be different between ARM9 (which I use) and ARM11?

Thinking about it this rings a bell. I know it behaves like described on ARM9,
so code executing in TCM can only "see" physical memory.

But one difference between the ARM9 and ARM11 families is that the cache
is mapped to virtual (MMU:ed) address space in ARM9 and to physical address
space in ARM11 is it not? (Is this so already in ARM10 BTW?)

So just thinking intuitively about it, as a TCM memory is very close to what
a cache is to the CPU I think it's something like this on ARM9:

     CPU
     / \
Cache   TCM
  |      |
 MMU     |
  |      |
External memory interface

But on ARM11 (ARM10?):

     CPU
      |
     MMU
     / \
Cache   TCM
  |
External memory interface

Is that correct more or less? Catalin would you happen to know this?

I think you are right. 

Anyway the code should still work actually, since we make a 1-1 memory
map anyway. But you cannot place the TCM in the memory locations I
chose for U300 since these are occupied on ARM11.

Sorry, I haven't tried your patch at kernel, I just did experiments at u-boot.

Linus Walleij

-- 
Best Regards
Peter Chen