On Thu, Jun 19, 2025 at 05:10:50PM +0200, Peter Zijlstra wrote:
On Thu, Jun 19, 2025 at 08:00:30AM -0700, Boqun Feng wrote:
quoted
quoted
So given we build locks from atomics, this has to come from somewhere.
The simplest lock -- TAS -- is: rmw.acquire + store.release.
So while plain store.release + load.acquire might not make TSO (although
IIRC ARM added variants that do just that in an effort to aid x86
emulation); store.release + rmw.acquire must, otherwise we cannot
satisfy that unlock+lock.
Make sense, so something like this in the model should work:
diff --git a/tools/memory-model/linux-kernel.cat b/tools/memory-model/linux-kernel.cat
index d7e7bf13c831..90cb6db6e335 100644
--- a/tools/memory-model/linux-kernel.cat
+++ b/tools/memory-model/linux-kernel.cat
@@ -27,7 +27,7 @@ include "lock.cat"
(* Release Acquire *)
let acq-po = [Acquire] ; po ; [M]
let po-rel = [M] ; po ; [Release]
-let po-unlock-lock-po = po ; [UL] ; (po|rf) ; [LKR] ; po
+let po-unlock-lock-po = po ; (([UL] ; (po|rf) ; [LKR]) | ([Release]; (po;rf); [Acquire & RMW])) ; po
(* Fences *)
let R4rmb = R \ Noreturn (* Reads for which rmb works *)
I am forever struggling with cats, but that does look about right :-)
;-) ;-) ;-)
quoted
although I'm not sure whether there will be actual users that use this
ordering.
include/asm-generic/ticket_spinlock.h comes to mind, as I thing would
kernel/locking/qspinlock.*, no?
Ah, right. Although I thought users outside lock implementation would be
nice, but you're right, we do have users. Previously our reasoning for
correctness of this particular locking ordering kinda depends on
per-architecture memory model reasoning, so modeling this does make
sense.
Regards,
Boqun