[PATCH 4/6] MIPS: tx39: fix tx39_flush_cache_page
From: Huang Pei <hidden>
Date: 2021-11-23 07:52:42
Also in:
linux-mips, linux-mm
Subsystem:
mips, the rest · Maintainers:
Thomas Bogendoerfer, Linus Torvalds
Indexed cache operation need KSEG0 address for safety and assume that no dcache alias nor high memory, since indexed cache instrcution CAN NOT handle cache alias Signed-off-by: Huang Pei <redacted> --- arch/mips/mm/c-tx39.c | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/arch/mips/mm/c-tx39.c b/arch/mips/mm/c-tx39.c
index 03dfbb40ec73..c7c3dbfe7756 100644
--- a/arch/mips/mm/c-tx39.c
+++ b/arch/mips/mm/c-tx39.c@@ -170,6 +170,7 @@ static void tx39_flush_cache_page(struct vm_area_struct *vma, unsigned long page struct mm_struct *mm = vma->vm_mm; pmd_t *pmdp; pte_t *ptep; + unsigned long vaddr = phys_to_virt(pfn_to_phys(pfn)); /* * If ownes no valid ASID yet, cannot possibly have gotten
@@ -207,11 +208,14 @@ static void tx39_flush_cache_page(struct vm_area_struct *vma, unsigned long page /* * Do indexed flush, too much work to get the (possible) TLB refills * to work correctly. + * + * Assuming that tx39 family do not support high memory, nor has + * dcache alias, vaddr can index dcache directly and correctly */ - if (cpu_has_dc_aliases || exec) - tx39_blast_dcache_page_indexed(page); - if (exec) - tx39_blast_icache_page_indexed(page); + if (exec) { + tx39_blast_dcache_page_indexed(vaddr); + tx39_blast_icache_page_indexed(vaddr); + } } static void local_tx39_flush_data_cache_page(void * addr)
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2.20.1