On Fri, Aug 13, 2021 at 10:14 AM Huacai Chen [off-list ref] wrote:

On Fri, Aug 13, 2021 at 3:05 PM Arnd Bergmann [off-list ref] wrote:

quoted

I still don't see what is special about 40 and 48. From what I can tell,
you have two constraints: the maximum address space size for
the kernel configuration based on the page size and number of
page table levels, and the capabilities of the CPU as described
in the CPUCFG1 register.

What is the point of introducing an arbitrary third compile-time
limit here rather than calculating it from the page page size?

So your problem is why we should provide two configurations VA40 and
VA48? This is derived from MIPS of course, but I found that RISC-V and
ARM64 also provide VA BITS configuration.

The difference is that on arm64 and riscv, the CONFIG_VA_BITS
configuration is directly derived from the page table layout.

E.g. when using 16K pages on arm64, you have the choice between
47 bits and 36 bits, while your method would apparently force going
to 40 bits and either waste most of the theoretically available address
space, or require three-level tables even if you only need 36 bits.

        Arnd