Re: [PATCH 04/19] LoongArch: Add common headers
From: Peter Zijlstra <peterz@infradead.org>
Date: 2021-07-06 10:57:21
On Tue, Jul 06, 2021 at 12:18:05PM +0800, Huacai Chen wrote:
quoted hunk
diff --git a/arch/loongarch/include/asm/barrier.h b/arch/loongarch/include/asm/barrier.h new file mode 100644 index 000000000000..8ab8d8f15b88 --- /dev/null +++ b/arch/loongarch/include/asm/barrier.h@@ -0,0 +1,53 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2020-2021 Loongson Technology Corporation Limited + */ +#ifndef __ASM_BARRIER_H +#define __ASM_BARRIER_H + +#include <asm/addrspace.h> + +#define __sync() __asm__ __volatile__("dbar 0" : : : "memory") + +#define fast_wmb() __sync() +#define fast_rmb() __sync() +#define fast_mb() __sync() +#define fast_iob() __sync() +#define wbflush() __sync() + +#define wmb() fast_wmb() +#define rmb() fast_rmb() +#define mb() fast_mb() +#define iob() fast_iob()
Is there any actual documentation about memory ordering for this architecture? Or are you going to do the MIPS trainwreck? Having a single full memory barrier for everything is very sad for a new architecture, we're in 2021, not 1990s.