Re: [PATCH v5 02/16] x86/cache: get cache size/leaves and setup cache cpumap for Dhyana
From: Borislav Petkov <bp@alien8.de>
Date: 2018-09-03 09:56:26
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From: Borislav Petkov <bp@alien8.de>
Date: 2018-09-03 09:56:26
Also in:
lkml
Patch subject needs to be of the format: <file path(s)>: Sentence starting with a capital letter and describing concisely the patch Fix all your subjects pls. On Wed, Aug 29, 2018 at 08:43:10PM +0800, Pu Wen wrote:
Hygon Dhyana processor has the topology extensions bit in CPUID. With this bit kernel can get the cache info. So add support
"With this bit, the kernel... "
in cpuid4_cache_lookup_regs() to get the correct cache size. Dhyana also find num_cache_leaves via CPUID leaf 0x8000001d, so
"... also discovers num_cache_leaves ..."
add Hygon support in find_num_cache_leaves(). Also add cacheinfo_hygon_init_llc_id() and init_hygon_cacheinfo() functions to initialize Dhyana cache info. Setup cache cpumap in the same way as AMD does. Signed-off-by: Pu Wen <puwen@hygon.cn> --- arch/x86/include/asm/cacheinfo.h | 1 + arch/x86/kernel/cpu/cacheinfo.c | 31 +++++++++++++++++++++++++++++-- arch/x86/kernel/cpu/cpu.h | 1 + arch/x86/kernel/cpu/hygon.c | 3 +++ 4 files changed, 34 insertions(+), 2 deletions(-)
With that:
Reviewed-by: Borislav Petkov <redacted>
--
Regards/Gruss,
Boris.
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