Re: mips octeon memory model questions
From: Peter Zijlstra <peterz@infradead.org>
Date: 2014-02-04 19:40:00
Also in:
linux-mips, lkml
From: Peter Zijlstra <peterz@infradead.org>
Date: 2014-02-04 19:40:00
Also in:
linux-mips, lkml
On Tue, Feb 04, 2014 at 11:16:58AM -0800, Linus Torvalds wrote:
On Tue, Feb 4, 2014 at 11:05 AM, Peter Zijlstraquoted
quoted
So writes move down, not up.Right, but the ll-sc store might move down over a later store.Unlikely. The thing is, in order for the sc to succeed, it has to already have hit the cache coherency domain (or at least reserved it - ie maybe the value is not actually *in* the cache, but the sc needs to have gotten exclusive access to the cacheline). So just how do you expect a later store (that is *after* the conditional branch that tests the result of the sc) to move up before it?
Ah, I completely overlooked the control dependency to the subsequent store. Yes, given that this makes sense.