On Tue, Feb 13, 2018 at 3:24 AM, Wu Hao [off-list ref] wrote:
Hi Hao,
Looks good.
From: Kang Luwei <redacted>
The Header Register set is always present for FPGA Management Engine (FME),
this patch implements init and uinit function for header sub feature and
introduce several read-only sysfs interfaces for the capability and status.
Sysfs interfaces:
* /sys/class/fpga_region/<regionX>/<dfl-fme.x>/ports_num
Read-only. Number of ports implemented
* /sys/class/fpga_region/<regionX>/<dfl-fme.x>/bitstream_id
Read-only. Blue Bitstream (static FPGA region) identifier number. It contains
the detailed version and other information of this static FPGA region.
* /sys/class/fpga_region/<regionX>/<dfl-fme.x>/bitstream_metadata
Read-only. Blue Bitstream (static FPGA region) meta data. It contains the
synthesis date, seed and other information of this static FPGA region.
Signed-off-by: Tim Whisonant <redacted>
Signed-off-by: Enno Luebbers <redacted>
Signed-off-by: Shiva Rao <redacted>
Signed-off-by: Christopher Rauer <redacted>
Signed-off-by: Kang Luwei <redacted>
Signed-off-by: Xiao Guangrong <guangrong.xiao-VuQAYsv1563Yd54FQh9/CA@public.gmane.org>
Signed-off-by: Wu Hao <redacted>
Acked-by: Alan Tull <redacted>
Thanks,
Alan