Thread (255 messages) 255 messages, 11 authors, 2021-10-29

RE: [RFC 10/20] iommu/iommufd: Add IOMMU_DEVICE_GET_INFO

From: "Tian, Kevin" <kevin.tian@intel.com>
Date: 2021-10-14 08:02:11
Also in: lkml

From: Jean-Philippe Brucker <redacted>
Sent: Thursday, September 30, 2021 6:33 PM

The PTE flags define whether the memory access is cache-coherent or not.
* WB is cacheable (short for write-back cacheable. Doesn't matter here
  what OI or RWA mean.)
* NC is non-cacheable.

         | Normal PCI access | No_snoop PCI access
  -------+-------------------+-------------------
  PTE WB | Cacheable         | Non-cacheable
  PTE NC | Non-cacheable     | Non-cacheable
This implies that PCI no-snoop supersedes PTE flags when it's supported
by the system?
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