Thread (4 messages) 4 messages, 2 authors, 2011-12-13

memory barrier in UP

From: subin gangadharan <hidden>
Date: 2011-12-12 18:57:11

Hi Mulyadi,

Thanks for the answer.

On Mon, Dec 12, 2011 at 11:16 AM, Mulyadi Santosa
[off-list ref] wrote:
Hi...

On Mon, Dec 12, 2011 at 01:11, subin gangadharan
[off-list ref] wrote:
quoted
Hi All,

I am reading about the barrier from linux kernel development.In this
books, he says
"On SMP kernels they are defined only as usual memory barriers.where
as on UP kernels they are
defined only as a compiler barrier"

Does this mean in UP, processor won't reorder the instructions ?
In some arch like Alpha, loosely reordering even in UP could happen at
any time. But in x86 UP, IIRC there's only strict re-ordering, meaning
that every read is always fetching latest write etc.
In that case (ALPHA), is compiler barrier sufficient enough to prevent
the re ordering done by the processor.
What I was thinking,compiler barrier is to instruct the compiler to
not do any re ordering.

Please correct me if I am wrong.
--
regards,

Mulyadi Santosa
Freelance Linux trainer and consultant

blog: the-hydra.blogspot.com
training: mulyaditraining.blogspot.com


-- 
With Regards
Subin Gangadharan

I am not afraid and I am also not afraid of being afraid.
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