On Aug 6, 2011 1:57 PM, "Mulyadi Santosa" [off-list ref] wrote:

On Sat, Aug 6, 2011 at 23:59, subin gangadharan
[off-list ref] wrote:

quoted

Hi All,
I have some doubts on the alignment requirement.It would be really
helpful,if someone can shed some light on this.
Why there are so many different types of alignment like 4 byte, 8

byte,16

quoted

byte ?.My exact question is, in a 32 bit machine(I assume processor

reads

quoted

data in 4 bytes),how 16 byte alignment makes different from 4 byte

alignment

quoted

?.How this will influence the processor performance ?.

personal guess: cache line alignment?

... so the data all can be read in one read swipe.....

or in other hand, if several data has different access type (some are
read only, the rest are read/write), then by aligning them to
different cache line, they won't interfere to each other...since AFAIK
a write to  even one bit in a cache line will update the whole cache
line. Other data in the same cache line will stay, they will be just
rewritten AFAIK.

I hope my guess is right :)

Too complex I think.   Don't try to think so hard. ;-)

Most cpu's offer an atomic test_and_set instruction.

It is used to write busy loop semaphore code like.

     While (test_and_set(flag) == false);
# coded in assembly

Normally that busy loops until flag initially has a value of zero during the
test and the test changes it to a one.

But if test_and_set always fails due lack of alignment, that loop will never
finish.

Greg
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