[PATCH 1/3] lib/amdgpu: Use correct SDMA doorbell offset for userqueues
From: Jesse Zhang <hidden>
Date: 2026-06-05 06:04:53
Subsystem:
library code, the rest · Maintainers:
Andrew Morton, Linus Torvalds
SDMA doorbell writes must target the per-page sub-aperture at qword offset 0x100 (dword offset 0x200) within any 4K doorbell page. Using the generic DOORBELL_INDEX (4) leads to incorrect ringing and non-functional SDMA userqueues. Define SDMA_DOORBELL_INDEX accordingly and apply it during queue creation and submission for AMD_IP_DMA. Signed-off-by: Jesse Zhang <redacted> --- lib/amdgpu/amd_ip_blocks.c | 11 +++++++++-- lib/amdgpu/amd_ip_blocks.h | 3 +++ 2 files changed, 12 insertions(+), 2 deletions(-)
diff --git a/lib/amdgpu/amd_ip_blocks.c b/lib/amdgpu/amd_ip_blocks.c
index 80aa5569c..b44441d0d 100644
--- a/lib/amdgpu/amd_ip_blocks.c
+++ b/lib/amdgpu/amd_ip_blocks.c@@ -748,7 +748,12 @@ user_queue_submit(amdgpu_device_handle device, struct amdgpu_ring_context *ring_ #if DETECT_CC_GCC && (DETECT_ARCH_X86 || DETECT_ARCH_X86_64) asm volatile ("mfence" : : : "memory"); #endif - ring_context->doorbell_cpu[DOORBELL_INDEX] = *ring_context->wptr_cpu; + if (ip_type == AMD_IP_DMA) { + /* Ring the SDMA doorbell at the page-modulo SDMA sub-aperture. */ + ring_context->doorbell_cpu[SDMA_DOORBELL_INDEX] = *ring_context->wptr_cpu; + } else { + ring_context->doorbell_cpu[DOORBELL_INDEX] = *ring_context->wptr_cpu; + } switch (ring_context->submit_mode) { case UQ_SUBMIT_NO_SYNC:
@@ -1006,8 +1011,10 @@ user_queue_create(amdgpu_device_handle device_handle, struct amdgpu_ring_context break; case AMD_IP_DMA: + /* Per-page BIF decode verified: standard userqueue path with + * doorbell_offset placed in any 4K page's SDMA sub-aperture. */ r = amdgpu_create_userqueue(device_handle, AMDGPU_HW_IP_DMA, - ctxt->db_handle, DOORBELL_INDEX, + ctxt->db_handle, SDMA_DOORBELL_INDEX, ctxt->queue.mc_addr, USERMODE_QUEUE_SIZE, ctxt->wptr.mc_addr, ctxt->rptr.mc_addr, mqd, queue_flags, &ctxt->queue_id);
diff --git a/lib/amdgpu/amd_ip_blocks.h b/lib/amdgpu/amd_ip_blocks.h
index eb118c68a..e26ee68a9 100644
--- a/lib/amdgpu/amd_ip_blocks.h
+++ b/lib/amdgpu/amd_ip_blocks.h@@ -60,6 +60,9 @@ #define USERMODE_QUEUE_SIZE (PAGE_SIZE * 256) //In bytes with total size as 1 Mbyte #define ALIGNMENT 4096 #define DOORBELL_INDEX 4 +/* SDMA per-page sub-aperture starts at dword 0x200 within any 4K page. + * In qword units (USERQ doorbell_offset is qword-indexed): 0x100. */ +#define SDMA_DOORBELL_INDEX 0x100 #define USERMODE_QUEUE_SIZE_DW (USERMODE_QUEUE_SIZE >> 2) #define USERMODE_QUEUE_SIZE_DW_MASK (USERMODE_QUEUE_SIZE_DW - 1)
--
2.49.0