[PATCH v4 08/10] drm/i915/alpm: Enable MAC Transmitting LFPS for LT PHY
From: Animesh Manna <hidden>
Date: 2025-11-13 12:29:17
Also in:
intel-gfx, intel-xe
Subsystem:
drm drivers, intel drm display for xe and i915 drivers, intel drm i915 driver (meteor lake, dg2 and older excluding poulsbo, moorestown and derivative), the rest · Maintainers:
David Airlie, Simona Vetter, Jani Nikula, Rodrigo Vivi, Joonas Lahtinen, Tvrtko Ursulin, Linus Torvalds
Enable MAC to transmit LFPS via LT PHY during aux-less alpm. v2: - Correct commit description. [Suraj] - Remove loop as no dependency on the transmitter LT_PHY_CMN_CTL0. [Suraj] v3: Cosmetic changes. [Suraj] Cc: Jouni Högander <redacted> Reviewed-by: Suraj Kandpal <redacted> Signed-off-by: Animesh Manna <redacted> --- drivers/gpu/drm/i915/display/intel_ddi.c | 5 +++- drivers/gpu/drm/i915/display/intel_lt_phy.c | 27 +++++++++++++++++++ drivers/gpu/drm/i915/display/intel_lt_phy.h | 2 ++ .../gpu/drm/i915/display/intel_lt_phy_regs.h | 3 +++ 4 files changed, 36 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 002ccd47856d..89ce3d13246a 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c@@ -3777,7 +3777,10 @@ static void mtl_ddi_prepare_link_retrain(struct intel_dp *intel_dp, * ii. Enable MAC Transmits LFPS in the "PHY Common Control 0" PIPE * register */ - intel_lnl_mac_transmit_lfps(encoder, crtc_state); + if (HAS_LT_PHY(display)) + intel_xe3plpd_mac_transmit_lfps(encoder, crtc_state); + else + intel_lnl_mac_transmit_lfps(encoder, crtc_state); } static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp,
diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c b/drivers/gpu/drm/i915/display/intel_lt_phy.c
index a67eb4f7f897..a1a5aed116b7 100644
--- a/drivers/gpu/drm/i915/display/intel_lt_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c@@ -6,6 +6,7 @@ #include <drm/drm_print.h> #include "i915_reg.h" +#include "intel_alpm.h" #include "intel_cx0_phy.h" #include "intel_cx0_phy_regs.h" #include "intel_ddi.h"
@@ -2325,3 +2326,29 @@ void intel_xe3plpd_pll_disable(struct intel_encoder *encoder) intel_lt_phy_pll_disable(encoder); } + +/* + * According to HAS we need to enable MAC Transmitting LFPS in the "PHY Common + * Control 0" PIPE register in case of AUX Less ALPM is going to be used. This + * function is doing that and is called by link retrain sequence. + */ +void intel_xe3plpd_mac_transmit_lfps(struct intel_encoder *encoder, + const struct intel_crtc_state *crtc_state) +{ + struct intel_dp *intel_dp = enc_to_intel_dp(encoder); + intel_wakeref_t wakeref; + u8 owned_lane_mask; + + if (!intel_alpm_is_alpm_aux_less(intel_dp, crtc_state)) + return; + + wakeref = intel_lt_phy_transaction_begin(encoder); + + owned_lane_mask = intel_lt_phy_get_owned_lane_mask(encoder); + + intel_lt_phy_rmw(encoder, owned_lane_mask, LT_PHY_CMN_CTL_0, + LT_PHY_CMN_LFPS_ENABLE, + LT_PHY_CMN_LFPS_ENABLE, MB_WRITE_COMMITTED); + + intel_lt_phy_transaction_end(encoder, wakeref); +}
diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.h b/drivers/gpu/drm/i915/display/intel_lt_phy.h
index b7911acd7dcd..5cea01b1756a 100644
--- a/drivers/gpu/drm/i915/display/intel_lt_phy.h
+++ b/drivers/gpu/drm/i915/display/intel_lt_phy.h@@ -41,6 +41,8 @@ intel_lt_phy_calculate_hdmi_state(struct intel_lt_phy_pll_state *lt_state, void intel_xe3plpd_pll_enable(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state); void intel_xe3plpd_pll_disable(struct intel_encoder *encoder); +void intel_xe3plpd_mac_transmit_lfps(struct intel_encoder *encoder, + const struct intel_crtc_state *crtc_state); #define HAS_LT_PHY(display) (DISPLAY_VER(display) >= 35)
diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h b/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h
index 98ccc069a69b..c50dbad28b78 100644
--- a/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h@@ -35,6 +35,9 @@ #define LT_PHY_TXY_CTL10_MAC(idx) _MMIO(LT_PHY_TXY_CTL10(idx)) #define LT_PHY_TX_LANE_ENABLE REG_BIT8(0) +#define LT_PHY_CMN_CTL_0 (0x800) +#define LT_PHY_CMN_LFPS_ENABLE REG_BIT8(1) + /* LT Phy Vendor Register */ #define LT_PHY_VDR_0_CONFIG 0xC02 #define LT_PHY_VDR_DP_PLL_ENABLE REG_BIT(7)
--
2.29.0