On Wed, Jun 16, 2021 at 01:29:24PM +0000, Zhang, Qi Z wrote:

Hi

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-----Original Message-----
From: Honnappa Nagarahalli <redacted>
Sent: Tuesday, June 8, 2021 5:36 AM
To: Zhang, Qi Z <redacted>; Joyce Kong <redacted>;
Xing, Beilei [off-list ref]; Ruifeng Wang [off-list ref]
Cc: dev@dpdk.org; nd <redacted>; Honnappa Nagarahalli
[off-list ref]; nd [off-list ref]
Subject: RE: [PATCH v1] net/i40e: remove the SMP barrier in HW scanning
func

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Add the logic to determine how many DD bits have been set for
contiguous packets, for removing the SMP barrier while reading descs.

I didn't understand this.
The current logic already guarantee the read out DD bits are from
continue packets, as it read Rx descriptor in a reversed order
from the

ring.

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Qi, the comments in the code mention that there is a race condition
if the descriptors are not read in the reverse order. But, they do
not mention what the race condition is and how it can occur.
Appreciate if you could explain that.

The Race condition happens between the NIC and CPU, if write and read
DD bit in the same order, there might be a hole (e.g. 1011)  with the
reverse read order, we make sure no more "1" after the first "0"
as the read address are declared as volatile, compiler will not
re-ordered them.

My understanding is that

1) the NIC will write an entire cache line of descriptors to memory "atomically"
(i.e. the entire cache line is visible to the CPU at once) if there are enough
descriptors ready to fill one cache line.
2) But, if there are not enough descriptors ready (because for ex: there is not
enough traffic), then it might write partial cache lines.

Yes, for example a cache line contains 4 x16 bytes descriptors and it is possible we get 1 1 1 0 for DD bit at some moment.

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Please correct me if I am wrong.

For #1, I do not think it matters if we read the descriptors in reverse order or
not as the cache line is written atomically.

I think below cases may happens if we don't read in reserve order.

1. CPU get first cache line as 1 1 1 0 in a loop
2. new packets coming and NIC append last 1 to the first cache and a new cache line with 1 1 1 1.
3. CPU continue new cache line with 1 1 1 1 in the same loop, but the last 1 of first cache line is missed, so finally it get 1 1 1 0 1 1 1 1. 

The one-sentence answer here is: when two entities are moving along a line
in the same direction - like two runners in a race - then they can pass
each other multiple times as each goes slower or faster at any point in
time, whereas if they are moving in opposite directions there will only
ever be one cross-over point no matter how the speed of each changes. 

In the case of NIC and software this fact means that there will always be a
clear cross-over point from DD set to not-set.

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For #1, if we read in reverse order, does it make sense to not check the DD bits
of descriptors that are earlier in the order once we encounter a descriptor that
has its DD bit set? This is because NIC updates the descriptors in order.

I think the answer is yes, when we met the first DD bit, we should able to calculated the exact number base on the index, but not sure how much performance gain.

The other factors here are:
1. The driver does not do a straight read of all 32 DD bits in one go,
rather it does 8 at a time and aborts at the end of a set of 8 if not all
are valid.
2. For any that are set, we have to read the descriptor anyway to get the
packet data out of it, so in the shortcut case of the last descriptor being
set, we still have to read the other 7 anyway, and DD comes for free as
part of it.
3. Blindly reading 8 at a time reduces the branching to just a single
decision point at the end of each set of 8, reducing possible branch
mispredicts.