On Sat, 2019-01-05 at 22:47 +0000, Honnappa Nagarahalli wrote:

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On Fri, 2019-01-04 at 19:59 +0000, Yongseok Koh wrote:

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Hi,

The cacheline size (RTE_CACHE_LINE_SIZE) for ARM CPUs is set to be
128B by default. Mellanox's BlueField is an ARM CPU having
Cortex-A72
and its CL size is 64B.

Just wondering how many devices are out there with 128B cache line? I
also have not heard about any future devices with 128B cache line. If
the majority is 64B, why not keep 64B as the default?

The problem is, In the armv8 spec the cache line size is IMPLEMENTATION
DEFINED. Marvell's embedded processors has 128B CL and Server processors
has 64B CL.

Assuming the defconfig_arm64-armv8a-linuxapp-gcc will be used by distro
folks then that configuration should support all the devices with
armv8.1 spec. For instance, marvells new chips are armv8.2 but we can not
make that as default.

What will happen in the future when we will have v9, v10 etc? I think the distro(generic/binary portable) config should get rid of v8.

Target specific configuration can be used for optimized target specific
configuration.

Or any other ideas for distro config.

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I can add config/defconfig_arm64-bluefield-linuxapp-gcc for legacy
build anyway.

Makes sense.

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For the meson build, I know it parses the Main ID register to
figure
out Implementor ID and Part Number. However, Mellanox doesn't
program
our own ID yet but we set the Part Number as 0xd08 (A72).
According to my folks, ARM's A53, A57, A72, and A73 designs all
have
64B CL. If that's true, can I push a patch to make the change?

Yes. Broadcom Stingray has the same situation i.e Use
flags_generic,
machine_args_generic

This will solve only the native compilation issue. It will not
address distro compilation (may be this is not your goal?).

See above.

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Please comment.


Thanks,
Yongseok