On Thu, Jul 26, 2018 at 07:13:50PM -0700, Hui Liu wrote:

Hi Experts,

I'm developing my own dpdk-based application via Intel 82599ES port. My
Application is doing a job to send ICMP requests (packet size varies from
64 bytes to 1472 bytes, 200,000 pps, 1.1Gbps) and receive responses, with
ARP request/response and ICMP response handling when necessary. It was
working pretty fine in 5 hours to 10 days  randomly and then TX descriptors
run out and cannot be freed by ixgbe_tx_free_bufs() due to DD bit is not
set:

        /* check DD bit on threshold descriptor */
        status = txq->tx_ring[txq->tx_next_dd].wb.status;
        if (!(status & IXGBE_ADVTXD_STAT_DD))
                return 0;

My tx queue setup is:
        tx_conf->tx_thresh.pthresh = 64;
        tx_conf->tx_thresh.hthresh = 0;
        tx_conf->tx_thresh.wthresh = 0;
        tx_conf->tx_free_thresh = 256;
        tx_conf->tx_rs_thresh = 32;
        tx_conf->txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
ETH_TXQ_FLAGS_NOOFFLOADS;


I tried to read code to see if there is any case to take these descriptors
and never set IXGBE_ADVTXD_STAT_DD back but no luck yet. And I have not
even found the related code when IXGBE_ADVTXD_STAT_DD is set/unset when
descriptor is taken/released other than reset queues... So may I ask:
1. where do we set/unset IXGBE_ADVTXD_STAT_DD when descriptor is
taken/released?

For RX and TX, the DD bit is never set by software, only by hardware. When
writing a descriptor to memory for the NIC to read, the DD bit is cleared.
Software knows the NIC has finished with that descriptor by checking for
the DD bit being set by the NIC. If the DD bit is not being set, then the
problem is likely on the NIC side. [Potential software issues that could
cause this might be buffer e.g. overflows where we overwrite a DD bit set
by the NIC, or where we are polling an incorrect address, etc. etc.]

Regards,
/Bruce