On Fri, Mar 25, 2016 at 02:06:51PM +0000, Ananyev, Konstantin wrote:

quoted

-----Original Message-----
From: dev [mailto:dev-bounces@dpdk.org] On Behalf Of Olivier Matz
Sent: Friday, March 25, 2016 10:32 AM
To: dev@dpdk.org
Cc: Lu, Wenzhuo
Subject: [dpdk-dev] [PATCH] igb: fix crash with offload on 82575 chipset

On the 82575 chipset, there is a pool of global TX contexts instead of 2
per queues on 82576. See Table A-1 "Changes in Programming Interface
Relative to 82575" of Intel® 82576EB GbE Controller datasheet (*).

In the driver, the contexts are attributed to a TX queue: 0-1 for txq0,
2-3 for txq1, and so on.

In igbe_set_xmit_ctx(), the variable ctx_curr contains the index of the
per-queue context (0 or 1), and ctx_idx contains the index to be given
to the hardware (0 to 7). The size of txq->ctx_cache[] is 2, and must
be indexed with ctx_curr to avoid an out-of-bound access.

Also, the index returned by what_advctx_update() is the per-queue
index (0 or 1), so we need to add txq->ctx_start before sending it
to the hardware.

(*) The datasheets says 16 global contexts, however the IDX fields in TX
    descriptors are 3 bits, which gives a total of 8 contexts. The
    driver assumes there are 8 contexts on 82575: 2 per queues, 4 txqs.

Fixes: 4c8db5f09a ("igb: enable TSO support")
Fixes: af75078fec ("first public release")
Signed-off-by: Olivier Matz <redacted>

Acked-by: Konstantin Ananyev <redacted>

Applied to dpdk-next-net/rel_16_04

/Bruce