[PATCH v4 1/4] eal: Introduce new cache line macro definitions
From: Jerin Jacob <hidden>
Date: 2016-01-29 07:46:31
Subsystem:
library code, the rest · Maintainers:
Andrew Morton, Linus Torvalds
- RTE_CACHE_LINE_MIN_SIZE(Supported minimum cache line size) - __rte_cache_min_aligned(Force minimum cache line alignment) - RTE_CACHE_LINE_SIZE_LOG2(Express cache line size in terms of log2) Signed-off-by: Jerin Jacob <redacted> Suggested-by: Konstantin Ananyev <redacted> --- lib/librte_eal/common/include/rte_memory.h | 16 ++++++++++++++++ 1 file changed, 16 insertions(+)
diff --git a/lib/librte_eal/common/include/rte_memory.h b/lib/librte_eal/common/include/rte_memory.h
index 2200d58..f8dbece 100644
--- a/lib/librte_eal/common/include/rte_memory.h
+++ b/lib/librte_eal/common/include/rte_memory.h@@ -74,11 +74,27 @@ enum rte_page_sizes { (RTE_CACHE_LINE_SIZE * ((size + RTE_CACHE_LINE_SIZE - 1) / RTE_CACHE_LINE_SIZE)) /**< Return the first cache-aligned value greater or equal to size. */ +/**< Cache line size in terms of log2 */ +#if RTE_CACHE_LINE_SIZE == 64 +#define RTE_CACHE_LINE_SIZE_LOG2 6 +#elif RTE_CACHE_LINE_SIZE == 128 +#define RTE_CACHE_LINE_SIZE_LOG2 7 +#else +#error "Unsupported cache line size" +#endif + +#define RTE_CACHE_LINE_MIN_SIZE 64 /**< Minimum Cache line size. */ + /** * Force alignment to cache line. */ #define __rte_cache_aligned __rte_aligned(RTE_CACHE_LINE_SIZE) +/** + * Force minimum cache line alignment. + */ +#define __rte_cache_min_aligned __rte_aligned(RTE_CACHE_LINE_MIN_SIZE) + typedef uint64_t phys_addr_t; /**< Physical address definition. */ #define RTE_BAD_PHYS_ADDR ((phys_addr_t)-1)
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2.1.0