Re: [PATCH 5.10.y-cip 0/7] Add binding and SoC identification for Renesas... | cip-dev

[PATCH 5.10.y-cip 0/7] Add binding and SoC identification for Renesas RZ/G2L SoC and Renesas RZ/G2L SMARC EVK · Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> · 2021-12-15
[PATCH 5.10.y-cip 1/7] dt-bindings: arm: renesas: Document Renesas RZ/G2UL SoC · Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> · 2021-12-15
[PATCH 5.10.y-cip 2/7] dt-bindings: arm: renesas: Document Renesas RZ/G2{L,LC} SoC variants · Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> · 2021-12-15
[PATCH 5.10.y-cip 3/7] dt-bindings: arm: renesas: Document SMARC EVK · Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> · 2021-12-15
[PATCH 5.10.y-cip 6/7] soc: renesas: Add support to read LSI DEVID register of RZ/G2{L,LC} SoC's · Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> · 2021-12-15
[PATCH 5.10.y-cip 7/7] arm64: defconfig: Enable ARCH_R9A07G044 · Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> · 2021-12-15
[PATCH 5.10.y-cip 4/7] dt-bindings: power: renesas,rzg2l-sysc: Add DT binding documentation for SYSC controller · Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> · 2021-12-15
[PATCH 5.10.y-cip 5/7] soc: renesas: Add ARCH_R9A07G044 for the new RZ/G2L SoC's · Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> · 2021-12-15
Re: [PATCH 5.10.y-cip 0/7] Add binding and SoC identification for Renesas RZ/G2L SoC and Renesas RZ/G2L SMARC EVK · Pavel Machek <hidden> · 2021-12-15
RE: [PATCH 5.10.y-cip 0/7] Add binding and SoC identification for Renesas RZ/G2L SoC and Renesas RZ/G2L SMARC EVK · Prabhakar Mahadev Lad <prabhakar.mahadev-lad.rj@bp.renesas.com> · 2021-12-15
RE: [cip-dev] [PATCH 5.10.y-cip 0/7] Add binding and SoC identification for Renesas RZ/G2L SoC and Renesas RZ/G2L SMARC EVK · Chris Paterson <hidden> · 2021-12-15
Re: [cip-dev] [PATCH 5.10.y-cip 0/7] Add binding and SoC identification for Renesas RZ/G2L SoC and Renesas RZ/G2L SMARC EVK · <hidden> · 2021-12-16
RE: [cip-dev] [PATCH 5.10.y-cip 0/7] Add binding and SoC identification for Renesas RZ/G2L SoC and Renesas RZ/G2L SMARC EVK · Chris Paterson <hidden> · 2021-12-16
Re: [cip-dev] [PATCH 5.10.y-cip 0/7] Add binding and SoC identification for Renesas RZ/G2L SoC and Renesas RZ/G2L SMARC EVK · <hidden> · 2021-12-16
Re: [PATCH 5.10.y-cip 0/7] Add binding and SoC identification for Renesas RZ/G2L SoC and Renesas RZ/G2L SMARC EVK · <hidden> · 2021-12-16
Re: [PATCH 5.10.y-cip 0/7] Add binding and SoC identification for Renesas RZ/G2L SoC and Renesas RZ/G2L SMARC EVK · Pavel Machek <hidden> · 2021-12-16

Re: [PATCH 5.10.y-cip 0/7] Add binding and SoC identification for Renesas RZ/G2L SoC and Renesas RZ/G2L SMARC EVK

From: Pavel Machek <hidden>
Date: 2021-12-15 10:06:06

Hi!

This patch series adds initial support for Renesas RZ/G2L SoC [0] and
Renesas RZ/G2L SMARC EVK [1].

The RZ/G2L microprocessor includes a Cortex-A55 (1.2 GHz) CPU, 16-bit
DDR3L/DDR4 interface, 3D graphics engine with Arm Mali-G31 and video codec
(H.264). It also has many interfaces such as camera input, display output,
USB 2.0, and Gbit-Ether, making it ideal for applications such as
entry-class industrial human-machine interfaces (HMIs) and embedded devices
with video capabilities.

I have reviewed patches and they look okay to me. I'll proceed with
testing.

Do we have suitable board in the test lab / is there plan to add one?

Best regards,
								Pavel
-- 
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany

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