[cip-dev] [PATCH 5.10.y-cip 03/16] pinctrl: renesas: r8a7796: Optimize pinctrl image size for R8A774A1
From: "Lad Prabhakar" <prabhakar.mahadev-lad.rj@bp.renesas.com>
Date: 2021-06-21 17:09:34
Subsystem:
pin control subsystem, pin controller - renesas, the rest · Maintainers:
Linus Walleij, Geert Uytterhoeven, Linus Torvalds
From: Biju Das <biju.das.jz@bp.renesas.com> commit 74ce7a8044b07268817828af2d6268801ddc012b upstream. This driver supports both RZ/G2M and R-Car M3-W/W+ SoCs. Optimize pinctrl image size for RZ/G2M, when support for R-Car M3-W/W+ (R8A7796[01]) is not enabled. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20201019132805.5996-1-biju.das.jz@bp.renesas.com (local) Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> --- drivers/pinctrl/renesas/pfc-r8a7796.c | 12 ++++++++++++ 1 file changed, 12 insertions(+)
diff --git a/drivers/pinctrl/renesas/pfc-r8a7796.c b/drivers/pinctrl/renesas/pfc-r8a7796.c
index 55f0344a3d3e..88e9c46003d9 100644
--- a/drivers/pinctrl/renesas/pfc-r8a7796.c
+++ b/drivers/pinctrl/renesas/pfc-r8a7796.c@@ -1831,6 +1831,7 @@ static const unsigned int canfd1_data_mux[] = { CANFD1_TX_MARK, CANFD1_RX_MARK, }; +#if defined(CONFIG_PINCTRL_PFC_R8A77960) || defined(CONFIG_PINCTRL_PFC_R8A77961) /* - DRIF0 --------------------------------------------------------------- */ static const unsigned int drif0_ctrl_a_pins[] = { /* CLK, SYNC */
@@ -2045,6 +2046,7 @@ static const unsigned int drif3_data1_b_pins[] = { static const unsigned int drif3_data1_b_mux[] = { RIF3_D1_B_MARK, }; +#endif /* CONFIG_PINCTRL_PFC_R8A77960 || CONFIG_PINCTRL_PFC_R8A77961 */ /* - DU --------------------------------------------------------------------- */ static const unsigned int du_rgb666_pins[] = {
@@ -4133,7 +4135,9 @@ static const unsigned int vin5_clk_mux[] = { static const struct { struct sh_pfc_pin_group common[316]; +#if defined(CONFIG_PINCTRL_PFC_R8A77960) || defined(CONFIG_PINCTRL_PFC_R8A77961) struct sh_pfc_pin_group automotive[30]; +#endif } pinmux_groups = { .common = { SH_PFC_PIN_GROUP(audio_clk_a_a),
@@ -4453,6 +4457,7 @@ static const struct { SH_PFC_PIN_GROUP(vin5_clkenb), SH_PFC_PIN_GROUP(vin5_clk), }, +#if defined(CONFIG_PINCTRL_PFC_R8A77960) || defined(CONFIG_PINCTRL_PFC_R8A77961) .automotive = { SH_PFC_PIN_GROUP(drif0_ctrl_a), SH_PFC_PIN_GROUP(drif0_data0_a),
@@ -4485,6 +4490,7 @@ static const struct { SH_PFC_PIN_GROUP(drif3_data0_b), SH_PFC_PIN_GROUP(drif3_data1_b), } +#endif /* CONFIG_PINCTRL_PFC_R8A77960 || CONFIG_PINCTRL_PFC_R8A77961 */ }; static const char * const audio_clk_groups[] = {
@@ -4543,6 +4549,7 @@ static const char * const canfd1_groups[] = { "canfd1_data", }; +#if defined(CONFIG_PINCTRL_PFC_R8A77960) || defined(CONFIG_PINCTRL_PFC_R8A77961) static const char * const drif0_groups[] = { "drif0_ctrl_a", "drif0_data0_a",
@@ -4584,6 +4591,7 @@ static const char * const drif3_groups[] = { "drif3_data0_b", "drif3_data1_b", }; +#endif /* CONFIG_PINCTRL_PFC_R8A77960 || CONFIG_PINCTRL_PFC_R8A77961 */ static const char * const du_groups[] = { "du_rgb666",
@@ -4997,7 +5005,9 @@ static const char * const vin5_groups[] = { static const struct { struct sh_pfc_function common[50]; +#if defined(CONFIG_PINCTRL_PFC_R8A77960) || defined(CONFIG_PINCTRL_PFC_R8A77961) struct sh_pfc_function automotive[4]; +#endif } pinmux_functions = { .common = { SH_PFC_FUNCTION(audio_clk),
@@ -5051,12 +5061,14 @@ static const struct { SH_PFC_FUNCTION(vin4), SH_PFC_FUNCTION(vin5), }, +#if defined(CONFIG_PINCTRL_PFC_R8A77960) || defined(CONFIG_PINCTRL_PFC_R8A77961) .automotive = { SH_PFC_FUNCTION(drif0), SH_PFC_FUNCTION(drif1), SH_PFC_FUNCTION(drif2), SH_PFC_FUNCTION(drif3), } +#endif /* CONFIG_PINCTRL_PFC_R8A77960 || CONFIG_PINCTRL_PFC_R8A77961 */ }; static const struct pinmux_cfg_reg pinmux_config_regs[] = {
--
2.17.1