Hi Peter,

On 19.09.21 09:50, Peter Rosin wrote:

On 2021-09-19 09:06, Rouven Czerwinski wrote:

quoted

Hi Peter,

while this may break for your board, it fundamentally introduces the
possibility to speculate out of the RAM area on speculation happy

I'm aware of that. For me, speculation is not an issue since *any*
rogue code running on the embedded device in question is a major fail.

We have seen Cortex-A7 CPUs speculatively executing I/O memory. That's
why we mar everything eXecute-Never except for known memory banks and
expect board code to mark any further regions that are safe to execute
manually. 

Also, from the cover letter:

"I'm going to follow up with patches. I very much realize that
these patches are most likely not acceptable as-is, but I do
include them since they are probably the best description of
where the problems are."

quoted

processors. Are you calling into SAMA5D3 ROM code somewhere? If so an

*I* am not calling anything. Maybe the board code for sama5d3xek is,
but I have no idea as it's not "my" code. How can I figure out if it
does?

If you don't revert this patch. Do you get any output at all?
If not, enable DEBUG_LL and see how far you get before hanging.

Cheers,
Ahad

Cheers,
Peter

quoted

exception can be added similar to the handling for the HAB code
(arch/arm/cpu/mmu_early.c):

	if (IS_ENABLED(CONFIG_HABV4) && IS_ENABLED(CONFIG_ARCH_IMX6))
		map_region(0x0, SZ_1M, PMD_SECT_DEF_CACHED);

which allows calls into the NXP boot ROM to retrieve the HAB status.

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