The hardware requirements to perform a write leveling calibration are
not fulfilled by the Wandboard modules.
IMX6DQRM §44.11.6 "Write leveling Calibration" Note2 states that the first
bit of each data byte group (D0, D8, ..., D56) from memory must be connected
to the same data bus bit on the controller, which is not given on the
Wandboard modules, resulting in unpredictable calib results and breaking the
WBQUAD 2GiB SDRAM setup. Similar restrictions exist for the i.MX6SD.

Remove this calibration and use the MPWLDECTRL defaults.

Signed-off-by: Alexander Kurz <redacted>
---
 arch/arm/boards/technexion-wandboard/lowlevel.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/arch/arm/boards/technexion-wandboard/lowlevel.c b/arch/arm/boards/technexion-wandboard/lowlevel.c
index d3eb9a0..ff5ae6d 100644
--- a/arch/arm/boards/technexion-wandboard/lowlevel.c
+++ b/arch/arm/boards/technexion-wandboard/lowlevel.c

@@ -276,7 +276,6 @@ static unsigned long wandboard_dram_init(void)
 
 	__udelay(100);
 
-	mmdc_do_write_level_calibration();
 	mmdc_do_dqs_calibration();
 #ifdef DEBUG
 	mmdc_print_calibration_results();

-- 
2.1.4


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