On Fri, Nov 11, 2011 at 09:39:13AM +0200, Sasha Levin wrote:

On Fri, Nov 11, 2011 at 6:24 AM, Rusty Russell [off-list ref] wrote:

quoted

On Wed, 09 Nov 2011 22:57:28 +0200, Sasha Levin [off-list ref] wrote:

quoted

On Wed, 2011-11-09 at 22:52 +0200, Michael S. Tsirkin wrote:

quoted

On Wed, Nov 09, 2011 at 10:24:47PM +0200, Sasha Levin wrote:

quoted

It'll be a bit harder deprecating it in the future.

Harder than ... what ?

Harder than allowing devices not to present it at all if new layout
config is used. Right now the simple implementation is to use MMIO for
config and device specific, and let it fallback to legacy for ISR and
notifications (and therefore, this is probably how everybody will
implement it), which means that when you do want to deprecate legacy,
there will be extra work to be done then, instead of doing it now.

Indeed, I'd like to see two changes to your proposal:

(1) It should be all or nothing.  If a driver can find the virtio header
   capability, it should only use the capabilties.  Otherwise, it
   should fall back to legacy.  Your draft suggests a mix is possible;
   I prefer a clean failure (ie. one day don't present a BAR 0 *at
   all*, so ancient drivers just fail to load.).

(2) There's no huge win in keeping the same layout.  Let's make some
   cleanups.  There are more users ahead of us then behind us (I
   hope!).

Actually, if we already do cleanups, here are two more suggestions:

1. Make 64bit features a one big 64bit block, instead of having 32bits
in one place and 32 in another.
2. Remove the reserved fields out of the config (the ones that were
caused by moving the ISR and the notifications out).

quoted

But I think this is the right direction!

Thanks,
Rusty.

Also, an unrelated questions: With PIO, requests were ordered, which
means that if we wrote to the queue selector and then read from a
queue register we would read the correct queue info.
Is the same thing assured to us with MMIO?

For real PCI, reads do not bypass writes in PCI. However this
is only true if both are MMIO or both PIO reads.
I don't think the ordering of MMIO versus PIO is guaranteed.

On KVM, the kernel doesn't do anything to guarantee ordering.
So you get the natural ordering of the CPU.

If we write to a queue
selector and immediately read from queue info would we be reading the
right info, or is there the slight chance that it would get reordered
and we would be reading queue info first and writing to the selector
later?

The thing to realize is that write to queue selector with KVM is in the
end performed by host. And reading queue info means that host will be
reading the queue selector. So this is a write followed by read
from the same address. AFAIK no CPUs can reorder such accesses,
so you get the right info.

-- 
MST