Reviews by anup@brainfault.org · u-boot

All review-attestation trailers (Reviewed-by / Acked-by / Tested-by / Reported-by / Suggested-by / Co-developed-by / Reported-and-tested-by) by this address on the u-boot archive.

29 attestations . (29 Reviewed-by)

• DORMANTno replies REVIEWED: 5 (5M) Re: [PATCH 1/1] riscv: remove dram_init_banksize()
  2023-10-06 · Reviewed-by
• DORMANTno replies REVIEWED: 5 (5M) Re: [PATCH 1/1] RISC-V: CONFIG_SPL_OPENSBI_SCRATCH_OPTIONS description
  2023-07-05 · Reviewed-by
• STALE1435d REVIEWED: 5 (5M) Re: [PATCH] spl: opensbi: convert scratch options to config
  2022-08-08 · Reviewed-by
• STALE2255d REVIEWED: 5 (5M) [PATCH v7 22/22] doc: sifive: fu540: Add description for RISC-V FU540 U-Boot SPL
  2020-05-03 · Reviewed-by
• STALE2528d REVIEWED: 5 (5M) [U-Boot] [U-BOOT PATCH v1] riscv: sifive: fu540: set serial environment variable from otp
  2019-08-12 · Reviewed-by
• STALE2528d REVIEWED: 5 (5M) [U-Boot] [U-BOOT PATCH] riscv: sifive: fu540: set serial environment variable from otp
  2019-08-12 · Reviewed-by
• STALE2770d REVIEWED: 6 (5M) [U-Boot] [PATCH v5 25/25] riscv: Remove ae350.dts
  2018-12-12 · Reviewed-by
• STALE2770d REVIEWED: 6 (5M) [U-Boot] [PATCH v5 24/25] riscv: bootm: Change to use boot_hart from global data
  2018-12-12 · Reviewed-by
• STALE2770d REVIEWED: 6 (5M) [U-Boot] [PATCH v5 23/25] riscv: Save boot hart id to the global data
  2018-12-12 · Reviewed-by
• STALE2770d REVIEWED: 6 (5M) [U-Boot] [PATCH v5 22/25] riscv: Adjust the _exit_trap() position to come before handle_trap()
  2018-12-12 · Reviewed-by
• STALE2770d REVIEWED: 6 (5M) [U-Boot] [PATCH v5 21/25] riscv: Return to previous privilege level after trap handling
  2018-12-12 · Reviewed-by
• STALE2770d REVIEWED: 6 (5M) [U-Boot] [PATCH v5 20/25] riscv: Fix context restore before returning from trap handler
  2018-12-12 · Reviewed-by
• STALE2770d REVIEWED: 6 (5M) [U-Boot] [PATCH v5 19/25] riscv: Move trap handler codes to mtrap.S
  2018-12-12 · Reviewed-by
• STALE2770d REVIEWED: 6 (5M) [U-Boot] [PATCH v5 18/25] riscv: Do some basic architecture level cpu initialization
  2018-12-12 · Reviewed-by
• STALE2770d REVIEWED: 6 (5M) [U-Boot] [PATCH v5 17/25] riscv: Add indirect stringification to csr_xxx ops
  2018-12-12 · Reviewed-by
• STALE2770d REVIEWED: 6 (5M) [U-Boot] [PATCH v5 16/25] riscv: Update supports_extension() to use desc from cpu driver
  2018-12-12 · Reviewed-by
• STALE2770d REVIEWED: 6 (5M) [U-Boot] [PATCH v5 15/25] riscv: Add exception codes for xcause register
  2018-12-12 · Reviewed-by
• STALE2770d REVIEWED: 6 (5M) [U-Boot] [PATCH v5 14/25] riscv: Add CSR numbers
  2018-12-12 · Reviewed-by
• STALE2770d REVIEWED: 6 (5M) [U-Boot] [PATCH v5 13/25] riscv: Remove non-DM version of print_cpuinfo()
  2018-12-12 · Reviewed-by
• STALE2770d REVIEWED: 6 (5M) [U-Boot] [PATCH v5 12/25] riscv: Probe cpus during boot
  2018-12-12 · Reviewed-by
• STALE2770d REVIEWED: 6 (5M) [U-Boot] [PATCH v5 11/25] riscv: Enlarge the default SYS_MALLOC_F_LEN
  2018-12-12 · Reviewed-by
• STALE2770d REVIEWED: 6 (5M) [U-Boot] [PATCH v5 10/25] riscv: qemu: Add platform-specific Kconfig options
  2018-12-12 · Reviewed-by
• STALE2770d REVIEWED: 6 (5M) [U-Boot] [PATCH v5 08/25] riscv: Add a SYSCON driver for SiFive's Core Local Interruptor
  2018-12-12 · Reviewed-by
• STALE2770d REVIEWED: 6 (5M) [U-Boot] [PATCH v5 05/25] timer: Add generic driver for RISC-V privileged architecture defined timer
  2018-12-12 · Reviewed-by
• STALE2770d REVIEWED: 6 (5M) [U-Boot] [PATCH v5 04/25] cpu: Add a RISC-V CPU driver
  2018-12-12 · Reviewed-by
• STALE2770d REVIEWED: 6 (5M) [U-Boot] [PATCH v5 03/25] riscv: qemu: Create a simple-bus driver for the soc node
  2018-12-12 · Reviewed-by
• STALE2770d REVIEWED: 7 (6M) [U-Boot] [PATCH v5 02/25] dm: cpu: Add timebase frequency to the platdata
  2018-12-12 · Reviewed-by
• STALE2770d REVIEWED: 5 (5M) [U-Boot] [PATCH v5 01/25] riscv: add Kconfig entries for the code model
  2018-12-12 · Reviewed-by
• STALE2771d REVIEWED: 5 (5M) [U-Boot] [PATCH v4 00/25] riscv: Adding RISC-V CPU and timer driver
  2018-12-12 · Reviewed-by