[U-Boot] [PATCH 1/1 v2] ppc4xx: Reset and relock memory DLL after SDRAM_CLKTR change

After changing SDRAM_CLKTR phase value rerun the memory preload
initialization sequence (INITPLR) to reset and relock the memory
DLL. Changing the SDRAM_CLKTR memory clock phase coarse timing
adjustment effects the phase relationship of the internal, to the
PPC chip, and external, to the PPC chip, versions of MEMCLK_OUT.

Signed-off-by: Adam Graham <redacted>
Signed-off-by: Victor Gallardo <redacted>
---
 v2:
 - fix commit text. line to long.

 cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c |   21 +++++++++++++++++++++
 1 files changed, 21 insertions(+), 0 deletions(-)

diff --git a/cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c b/cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c
index 83b9883..47ab39b 100644
--- a/cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c
+++ b/cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c

@@ -174,6 +174,23 @@ static inline void ecc_clear_status_reg(void)
 #endif
 }
 
+/*
+ * Reset and relock memory DLL after SDRAM_CLKTR change
+ */
+static inline void relock_memory_DLL(void)
+{
+	u32 reg;
+
+	mtsdram(SDRAM_MCOPT2, SDRAM_MCOPT2_IPTR_EXECUTE);
+
+	do {
+		mfsdram(SDRAM_MCSTAT, reg);
+	} while (!(reg & SDRAM_MCSTAT_MIC_COMP));
+
+	mfsdram(SDRAM_MCOPT2, reg);
+	mtsdram(SDRAM_MCOPT2, reg | SDRAM_MCOPT2_DCEN_ENABLE);
+}
+
 static int ecc_check_status_reg(void)
 {
 	u32 ecc_status;

@@ -981,6 +998,8 @@ u32 DQS_autocalibration(void)
 
 		mtsdram(SDRAM_CLKTR, clkp << 30);
 
+		relock_memory_DLL();
+
 		putc('\b');
 		putc(slash[loopi++ % 8]);
 

@@ -1170,6 +1189,8 @@ u32 DQS_autocalibration(void)
 
 		mtsdram(SDRAM_CLKTR, tcal.clocks.clktr << 30);
 
+		relock_memory_DLL();
+
 		mfsdram(SDRAM_RQDC, rqdc_reg);
 		rqdc_reg &= ~(SDRAM_RQDC_RQFD_MASK);
 		mtsdram(SDRAM_RQDC, rqdc_reg |

-- 
1.5.5

On Monday 06 October 2008, Adam Graham wrote:

After changing SDRAM_CLKTR phase value rerun the memory preload
initialization sequence (INITPLR) to reset and relock the memory
DLL. Changing the SDRAM_CLKTR memory clock phase coarse timing
adjustment effects the phase relationship of the internal, to the
PPC chip, and external, to the PPC chip, versions of MEMCLK_OUT.

Applied ppc4xx/master. Thanks.

Best regards,
Stefan

=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80  Email: office at denx.de
=====================================================================

Adam,

On Wednesday 08 October 2008, Stefan Roese wrote:

On Monday 06 October 2008, Adam Graham wrote:

quoted

After changing SDRAM_CLKTR phase value rerun the memory preload
initialization sequence (INITPLR) to reset and relock the memory
DLL. Changing the SDRAM_CLKTR memory clock phase coarse timing
adjustment effects the phase relationship of the internal, to the
PPC chip, and external, to the PPC chip, versions of MEMCLK_OUT.

Applied ppc4xx/master. Thanks.

Ups. I just gave this version another try on my 600MHz Kilauea board. And as 
it seems it definitely works better than without this patch, but it doesn't 
work reliably. :-(

Here some outputs after rebooting:


U-Boot 2008.10-rc2-02708-gf8a00de (Oct  8 2008 - 11:40:49)

CPU:   AMCC PowerPC 405EX Rev. C at 600 MHz (PLB=200, OPB=100, EBC=100 MHz)
       Security support
       Bootstrap Option H - Boot ROM Location I2C (Addr 0x52)
       16 kB I-Cache 16 kB D-Cache
Board: Kilauea - AMCC PPC405EX Evaluation Board
I2C:   ready
DTT1:  FAILED
DRAM:  256 MB


U-Boot 2008.10-rc2-02708-gf8a00de (Oct  8 2008 - 11:40:49)

CPU:   AMCC PowerPC 405EX Rev. C at 600 MHz (PLB=200, OPB=100, EBC=100 MHz)
       Security support
       Bootstrap Option H - Boot ROM Location I2C (Addr 0x52)
       16 kB I-Cache 16 kB D-Cache
Board: Kilauea - AMCC PPC405EX Evaluation Board
I2C:   ready
DTT1:  FAILED
DRAM:  256 MB
Memory error at 01cff924, wrote 00000200, read aaaa0200 !


This didn't happen with the temporary patch you sent out a few weeks ago. This 
error occurs often after pushing the reset button on the Kilauea. I suggest 
that you take another look at this issue on your 600MHz board. Perhaps make a 
long test by setting "bootcmd" to "reset". If the board still resets after 
running for some hours, then you should be safe.

BTW: I won't ask Wolfgang to pull for now. 

Thanks.

Best regards,
Stefan

=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80  Email: office at denx.de
=====================================================================

Hi Stefan,
 
We will take a look. 
 
Yes, we ran the test as you mentioned (bootcmd=reset) on both versions of the Kilauea board and let it run for 24 hours without any problems. Hopefully we can reproduce the problem you are seeing.
 
Thanks,
 
Victor Gallardo

________________________________

From: Stefan Roese [mailto:sr at denx.de]
Sent: Wed 10/8/2008 2:47 AM
To: u-boot at lists.denx.de
Cc: Adam Graham; Victor Gallardo
Subject: Re: [U-Boot] [PATCH 1/1 v2] ppc4xx: Reset and relock memory DLL after SDRAM_CLKTR change



Adam,

On Wednesday 08 October 2008, Stefan Roese wrote:

On Monday 06 October 2008, Adam Graham wrote:

quoted

After changing SDRAM_CLKTR phase value rerun the memory preload
initialization sequence (INITPLR) to reset and relock the memory
DLL. Changing the SDRAM_CLKTR memory clock phase coarse timing
adjustment effects the phase relationship of the internal, to the
PPC chip, and external, to the PPC chip, versions of MEMCLK_OUT.

Applied ppc4xx/master. Thanks.

Ups. I just gave this version another try on my 600MHz Kilauea board. And as
it seems it definitely works better than without this patch, but it doesn't
work reliably. :-(

Here some outputs after rebooting:


U-Boot 2008.10-rc2-02708-gf8a00de (Oct  8 2008 - 11:40:49)

CPU:   AMCC PowerPC 405EX Rev. C at 600 MHz (PLB=200, OPB=100, EBC=100 MHz)
       Security support
       Bootstrap Option H - Boot ROM Location I2C (Addr 0x52)
       16 kB I-Cache 16 kB D-Cache
Board: Kilauea - AMCC PPC405EX Evaluation Board
I2C:   ready
DTT1:  FAILED
DRAM:  256 MB


U-Boot 2008.10-rc2-02708-gf8a00de (Oct  8 2008 - 11:40:49)

CPU:   AMCC PowerPC 405EX Rev. C at 600 MHz (PLB=200, OPB=100, EBC=100 MHz)
       Security support
       Bootstrap Option H - Boot ROM Location I2C (Addr 0x52)
       16 kB I-Cache 16 kB D-Cache
Board: Kilauea - AMCC PPC405EX Evaluation Board
I2C:   ready
DTT1:  FAILED
DRAM:  256 MB
Memory error at 01cff924, wrote 00000200, read aaaa0200 !


This didn't happen with the temporary patch you sent out a few weeks ago. This
error occurs often after pushing the reset button on the Kilauea. I suggest
that you take another look at this issue on your 600MHz board. Perhaps make a
long test by setting "bootcmd" to "reset". If the board still resets after
running for some hours, then you should be safe.

BTW: I won't ask Wolfgang to pull for now.

Thanks.

Best regards,
Stefan

=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80  Email: office at denx.de
=====================================================================