--- v9
+++ v2
@@ -1,183 +1,182 @@
From: Stefan Chulski <stefanc@marvell.com>
-This patch add PPv23 version definition.
-PPv23 is new packet processor in CP115.
-Everything that supported by PPv22, also supported by PPv23.
-No functional changes in this stage.
+Currently we have PP2v1 and PP2v2 hw-versions, with some different
+handlers depending upon condition hw_version = MVPP21/MVPP22.
+In a future there will be also PP2v3. Let's use now the generic
+"if equal/notEqual MVPP21" for all cases instead of "if MVPP22".
+
+This patch does not change any functionality.
+It is not intended to introduce PP2v3.
+It just modifies MVPP21/MVPP22 check-condition
+bringing it to generic and unified form correct for new-code
+introducing and PP2v3 net-next generation.
Signed-off-by: Stefan Chulski <stefanc@marvell.com>
---
- drivers/net/ethernet/marvell/mvpp2/mvpp2.h | 24 ++++++++++++--------
- drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c | 17 +++++++++-----
- 2 files changed, 25 insertions(+), 16 deletions(-)
+ drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c | 36 ++++++++++----------
+ 1 file changed, 18 insertions(+), 18 deletions(-)
-diff --git a/drivers/net/ethernet/marvell/mvpp2/mvpp2.h b/drivers/net/ethernet/marvell/mvpp2/mvpp2.h
-index 56e90ab..ce08086 100644
---- a/drivers/net/ethernet/marvell/mvpp2/mvpp2.h
-+++ b/drivers/net/ethernet/marvell/mvpp2/mvpp2.h
-@@ -60,6 +60,9 @@
- /* Top Registers */
- #define MVPP2_MH_REG(port) (0x5040 + 4 * (port))
- #define MVPP2_DSA_EXTENDED BIT(5)
-+#define MVPP2_VER_ID_REG 0x50b0
-+#define MVPP2_VER_PP22 0x10
-+#define MVPP2_VER_PP23 0x11
-
- /* Parser Registers */
- #define MVPP2_PRS_INIT_LOOKUP_REG 0x1000
-@@ -469,7 +472,7 @@
- #define MVPP22_GMAC_INT_SUM_MASK_LINK_STAT BIT(1)
- #define MVPP22_GMAC_INT_SUM_MASK_PTP BIT(2)
-
--/* Per-port XGMAC registers. PPv2.2 only, only for GOP port 0,
-+/* Per-port XGMAC registers. PPv2.2 and PPv2.3, only for GOP port 0,
- * relative to port->base.
- */
- #define MVPP22_XLG_CTRL0_REG 0x100
-@@ -506,7 +509,7 @@
- #define MVPP22_XLG_CTRL4_MACMODSELECT_GMAC BIT(12)
- #define MVPP22_XLG_CTRL4_EN_IDLE_CHECK BIT(14)
-
--/* SMI registers. PPv2.2 only, relative to priv->iface_base. */
-+/* SMI registers. PPv2.2 and PPv2.3, relative to priv->iface_base. */
- #define MVPP22_SMI_MISC_CFG_REG 0x1204
- #define MVPP22_SMI_POLLING_EN BIT(10)
-
-@@ -582,7 +585,7 @@
- #define MVPP2_QUEUE_NEXT_DESC(q, index) \
- (((index) < (q)->last_desc) ? ((index) + 1) : 0)
-
--/* XPCS registers. PPv2.2 only */
-+/* XPCS registers.PPv2.2 and PPv2.3 */
- #define MVPP22_MPCS_BASE(port) (0x7000 + (port) * 0x1000)
- #define MVPP22_MPCS_CTRL 0x14
- #define MVPP22_MPCS_CTRL_FWD_ERR_CONN BIT(10)
-@@ -593,7 +596,7 @@
- #define MVPP22_MPCS_CLK_RESET_DIV_RATIO(n) ((n) << 4)
- #define MVPP22_MPCS_CLK_RESET_DIV_SET BIT(11)
-
--/* XPCS registers. PPv2.2 only */
-+/* XPCS registers. PPv2.2 and PPv2.3 */
- #define MVPP22_XPCS_BASE(port) (0x7400 + (port) * 0x1000)
- #define MVPP22_XPCS_CFG0 0x0
- #define MVPP22_XPCS_CFG0_RESET_DIS BIT(0)
-@@ -927,15 +930,16 @@ struct mvpp2 {
- void __iomem *iface_base;
- void __iomem *cm3_base;
-
-- /* On PPv2.2, each "software thread" can access the base
-+ /* On PPv2.2 and PPv2.3, each "software thread" can access the base
- * register through a separate address space, each 64 KB apart
- * from each other. Typically, such address spaces will be
- * used per CPU.
- */
- void __iomem *swth_base[MVPP2_MAX_THREADS];
-
-- /* On PPv2.2, some port control registers are located into the system
-- * controller space. These registers are accessible through a regmap.
-+ /* On PPv2.2 and PPv2.3, some port control registers are located into
-+ * the system controller space. These registers are accessible
-+ * through a regmap.
- */
- struct regmap *sysctrl_base;
-
-@@ -977,7 +981,7 @@ struct mvpp2 {
- u32 tclk;
-
- /* HW version */
-- enum { MVPP21, MVPP22 } hw_version;
-+ enum { MVPP21, MVPP22, MVPP23 } hw_version;
-
- /* Maximum number of RXQs per port */
- unsigned int max_port_rxqs;
-@@ -1221,7 +1225,7 @@ struct mvpp21_rx_desc {
- __le32 reserved8;
- };
-
--/* HW TX descriptor for PPv2.2 */
-+/* HW TX descriptor for PPv2.2 and PPv2.3 */
- struct mvpp22_tx_desc {
- __le32 command;
- u8 packet_offset;
-@@ -1233,7 +1237,7 @@ struct mvpp22_tx_desc {
- __le64 buf_cookie_misc;
- };
-
--/* HW RX descriptor for PPv2.2 */
-+/* HW RX descriptor for PPv2.2 and PPv2.3 */
- struct mvpp22_rx_desc {
- __le32 status;
- __le16 reserved1;
diff --git a/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c b/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
-index e9c5916..5730900 100644
+index fc102f2..7143909 100644
--- a/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
+++ b/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
-@@ -384,7 +384,7 @@ static int mvpp2_bm_pool_create(struct device *dev, struct mvpp2 *priv,
- if (!IS_ALIGNED(size, 16))
- return -EINVAL;
+@@ -332,7 +332,7 @@ static int mvpp2_get_nrxqs(struct mvpp2 *priv)
+ {
+ unsigned int nrxqs;
-- /* PPv2.1 needs 8 bytes per buffer pointer, PPv2.2 needs 16
-+ /* PPv2.1 needs 8 bytes per buffer pointer, PPv2.2 and PPv2.3 needs 16
- * bytes per buffer pointer
- */
- if (priv->hw_version == MVPP21)
-@@ -1172,7 +1172,7 @@ static void mvpp2_interrupts_unmask(void *arg)
+- if (priv->hw_version == MVPP22 && queue_mode == MVPP2_QDIST_SINGLE_MODE)
++ if (priv->hw_version != MVPP21 && queue_mode == MVPP2_QDIST_SINGLE_MODE)
+ return 1;
+
+ /* According to the PPv2.2 datasheet and our experiments on
+@@ -459,7 +459,7 @@ static void mvpp2_bm_bufs_get_addrs(struct device *dev, struct mvpp2 *priv,
+ MVPP2_BM_PHY_ALLOC_REG(bm_pool->id));
+ *phys_addr = mvpp2_thread_read(priv, thread, MVPP2_BM_VIRT_ALLOC_REG);
+
+- if (priv->hw_version == MVPP22) {
++ if (priv->hw_version != MVPP21) {
+ u32 val;
+ u32 dma_addr_highbits, phys_addr_highbits;
+
+@@ -755,7 +755,7 @@ static inline void mvpp2_bm_pool_put(struct mvpp2_port *port, int pool,
+ if (test_bit(thread, &port->priv->lock_map))
+ spin_lock_irqsave(&port->bm_lock[thread], flags);
+
+- if (port->priv->hw_version == MVPP22) {
++ if (port->priv->hw_version != MVPP21) {
+ u32 val = 0;
+
+ if (sizeof(dma_addr_t) == 8)
+@@ -1212,7 +1212,7 @@ static bool mvpp2_port_supports_xlg(struct mvpp2_port *port)
+
+ static bool mvpp2_port_supports_rgmii(struct mvpp2_port *port)
+ {
+- return !(port->priv->hw_version == MVPP22 && port->gop_id == 0);
++ return !(port->priv->hw_version != MVPP21 && port->gop_id == 0);
+ }
+
+ /* Port configuration routines */
+@@ -1830,7 +1830,7 @@ static void mvpp2_mac_reset_assert(struct mvpp2_port *port)
+ MVPP2_GMAC_PORT_RESET_MASK;
+ writel(val, port->base + MVPP2_GMAC_CTRL_2_REG);
+
+- if (port->priv->hw_version == MVPP22 && port->gop_id == 0) {
++ if (port->priv->hw_version != MVPP21 && port->gop_id == 0) {
+ val = readl(port->base + MVPP22_XLG_CTRL0_REG) &
+ ~MVPP22_XLG_CTRL0_MAC_RESET_DIS;
+ writel(val, port->base + MVPP22_XLG_CTRL0_REG);
+@@ -1843,7 +1843,7 @@ static void mvpp22_pcs_reset_assert(struct mvpp2_port *port)
+ void __iomem *mpcs, *xpcs;
u32 val;
- int i;
-- if (port->priv->hw_version != MVPP22)
-+ if (port->priv->hw_version == MVPP21)
+- if (port->priv->hw_version != MVPP22 || port->gop_id != 0)
++ if (port->priv->hw_version == MVPP21 || port->gop_id != 0)
return;
- if (mask)
-@@ -5456,7 +5456,7 @@ static void mvpp2_rx_irqs_setup(struct mvpp2_port *port)
+ mpcs = priv->iface_base + MVPP22_MPCS_BASE(port->gop_id);
+@@ -1864,7 +1864,7 @@ static void mvpp22_pcs_reset_deassert(struct mvpp2_port *port)
+ void __iomem *mpcs, *xpcs;
+ u32 val;
+
+- if (port->priv->hw_version != MVPP22 || port->gop_id != 0)
++ if (port->priv->hw_version == MVPP21 || port->gop_id != 0)
return;
+
+ mpcs = priv->iface_base + MVPP22_MPCS_BASE(port->gop_id);
+@@ -4201,7 +4201,7 @@ static void mvpp2_start_dev(struct mvpp2_port *port)
+ /* Enable interrupts on all threads */
+ mvpp2_interrupts_enable(port);
+
+- if (port->priv->hw_version == MVPP22)
++ if (port->priv->hw_version != MVPP21)
+ mvpp22_mode_reconfigure(port);
+
+ if (port->phylink) {
+@@ -4417,7 +4417,7 @@ static int mvpp2_open(struct net_device *dev)
+ valid = true;
}
-- /* Handle the more complicated PPv2.2 case */
-+ /* Handle the more complicated PPv2.2 and PPv2.3 case */
- for (i = 0; i < port->nqvecs; i++) {
- struct mvpp2_queue_vector *qv = port->qvecs + i;
+- if (priv->hw_version == MVPP22 && port->port_irq) {
++ if (priv->hw_version != MVPP21 && port->port_irq) {
+ err = request_irq(port->port_irq, mvpp2_port_isr, 0,
+ dev->name, port);
+ if (err) {
+@@ -6065,7 +6065,7 @@ static int mvpp2__mac_prepare(struct phylink_config *config, unsigned int mode,
+ MVPP2_GMAC_PORT_RESET_MASK,
+ MVPP2_GMAC_PORT_RESET_MASK);
-@@ -5633,7 +5633,7 @@ static bool mvpp22_port_has_legacy_tx_irqs(struct device_node *port_node,
+- if (port->priv->hw_version == MVPP22) {
++ if (port->priv->hw_version != MVPP21) {
+ mvpp22_gop_mask_irq(port);
- /* Checks if the port dt description has the required Tx interrupts:
- * - PPv2.1: there are no such interrupts.
-- * - PPv2.2:
-+ * - PPv2.2 and PPv2.3:
- * - The old DTs have: "rx-shared", "tx-cpuX" with X in [0...3]
- * - The new ones have: "hifX" with X in [0..8]
- *
-@@ -6621,7 +6621,7 @@ static void mvpp22_rx_fifo_set_hw(struct mvpp2 *priv, int port, int data_size)
- mvpp2_write(priv, MVPP2_RX_ATTR_FIFO_SIZE_REG(port), attr_size);
- }
+ phy_power_off(port->comphy);
+@@ -6119,7 +6119,7 @@ static int mvpp2_mac_finish(struct phylink_config *config, unsigned int mode,
+ {
+ struct mvpp2_port *port = mvpp2_phylink_to_port(config);
--/* Initialize TX FIFO's: the total FIFO size is 48kB on PPv2.2.
-+/* Initialize TX FIFO's: the total FIFO size is 48kB on PPv2.2 and PPv2.3.
- * 4kB fixed space must be assigned for the loopback port.
- * Redistribute remaining avialable 44kB space among all active ports.
- * Guarantee minimum 32kB for 10G port and 8kB for port 1, capable of 2.5G
-@@ -6678,7 +6678,7 @@ static void mvpp22_tx_fifo_set_hw(struct mvpp2 *priv, int port, int size)
- mvpp2_write(priv, MVPP22_TX_FIFO_THRESH_REG(port), threshold);
- }
+- if (port->priv->hw_version == MVPP22 &&
++ if (port->priv->hw_version != MVPP21 &&
+ port->phy_interface != interface) {
+ port->phy_interface = interface;
--/* Initialize TX FIFO's: the total FIFO size is 19kB on PPv2.2.
-+/* Initialize TX FIFO's: the total FIFO size is 19kB on PPv2.2 and PPv2.3.
- * 3kB fixed space must be assigned for the loopback port.
- * Redistribute remaining avialable 16kB space among all active ports.
- * The 10G interface should use 10kB (which is maximum possible size
-@@ -7049,6 +7049,11 @@ static int mvpp2_probe(struct platform_device *pdev)
- priv->port_map |= BIT(i);
+@@ -6799,7 +6799,7 @@ static int mvpp2_init(struct platform_device *pdev, struct mvpp2 *priv)
+ if (dram_target_info)
+ mvpp2_conf_mbus_windows(dram_target_info, priv);
+
+- if (priv->hw_version == MVPP22)
++ if (priv->hw_version != MVPP21)
+ mvpp2_axi_init(priv);
+
+ /* Disable HW PHY polling */
+@@ -6959,7 +6959,7 @@ static int mvpp2_probe(struct platform_device *pdev)
+ dev_warn(&pdev->dev, "Fail to alloc CM3 SRAM\n");
}
+- if (priv->hw_version == MVPP22 && dev_of_node(&pdev->dev)) {
++ if (priv->hw_version != MVPP21 && dev_of_node(&pdev->dev)) {
+ priv->sysctrl_base =
+ syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
+ "marvell,system-controller");
+@@ -6972,7 +6972,7 @@ static int mvpp2_probe(struct platform_device *pdev)
+ priv->sysctrl_base = NULL;
+ }
+
+- if (priv->hw_version == MVPP22 &&
++ if (priv->hw_version != MVPP21 &&
+ mvpp2_get_nrxqs(priv) * 2 <= MVPP2_BM_MAX_POOLS)
+ priv->percpu_pools = 1;
+
+@@ -7019,7 +7019,7 @@ static int mvpp2_probe(struct platform_device *pdev)
+ if (err < 0)
+ goto err_pp_clk;
+
+- if (priv->hw_version == MVPP22) {
++ if (priv->hw_version != MVPP21) {
+ priv->mg_clk = devm_clk_get(&pdev->dev, "mg_clk");
+ if (IS_ERR(priv->mg_clk)) {
+ err = PTR_ERR(priv->mg_clk);
+@@ -7060,7 +7060,7 @@ static int mvpp2_probe(struct platform_device *pdev)
+ return -EINVAL;
+ }
+
+- if (priv->hw_version == MVPP22) {
+ if (priv->hw_version != MVPP21) {
-+ if (mvpp2_read(priv, MVPP2_VER_ID_REG) == MVPP2_VER_PP23)
-+ priv->hw_version = MVPP23;
-+ }
-+
- /* Initialize network controller */
- err = mvpp2_init(pdev, priv);
- if (err < 0) {
+ err = dma_set_mask(&pdev->dev, MVPP2_DESC_DMA_MASK);
+ if (err)
+ goto err_axi_clk;
+@@ -7140,10 +7140,10 @@ static int mvpp2_probe(struct platform_device *pdev)
+ clk_disable_unprepare(priv->axi_clk);
+
+ err_mg_core_clk:
+- if (priv->hw_version == MVPP22)
++ if (priv->hw_version != MVPP21)
+ clk_disable_unprepare(priv->mg_core_clk);
+ err_mg_clk:
+- if (priv->hw_version == MVPP22)
++ if (priv->hw_version != MVPP21)
+ clk_disable_unprepare(priv->mg_clk);
+ err_gop_clk:
+ clk_disable_unprepare(priv->gop_clk);
--
1.9.1