--- v9
+++ v4
@@ -1,137 +1,208 @@
From: Stefan Chulski <stefanc@marvell.com>
-New FIFO flow control feature was added in PPv23.
-PPv2 FIFO polled by HW and trigger pause frame if FIFO
-fill level is below threshold.
-FIFO HW flow control enabled with CM3 RXQ&BM flow
-control with ethtool.
-Current FIFO thresholds is:
-9KB for port with maximum speed 10Gb/s port
-4KB for port with maximum speed 5Gb/s port
-2KB for port with maximum speed 1Gb/s port
+This patch add RXQ flow control configurations.
+Patch do not enable flow control itself, flow control
+disabled by default.
Signed-off-by: Stefan Chulski <stefanc@marvell.com>
---
- drivers/net/ethernet/marvell/mvpp2/mvpp2.h | 15 ++++++
- drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c | 53 ++++++++++++++++++++
- 2 files changed, 68 insertions(+)
+ drivers/net/ethernet/marvell/mvpp2/mvpp2.h | 38 ++++++-
+ drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c | 111 ++++++++++++++++++++
+ 2 files changed, 146 insertions(+), 3 deletions(-)
diff --git a/drivers/net/ethernet/marvell/mvpp2/mvpp2.h b/drivers/net/ethernet/marvell/mvpp2/mvpp2.h
-index 9b525b60..b61a1ba 100644
+index e9625fb..934d535 100644
--- a/drivers/net/ethernet/marvell/mvpp2/mvpp2.h
+++ b/drivers/net/ethernet/marvell/mvpp2/mvpp2.h
-@@ -770,6 +770,18 @@
- #define MVPP2_TX_FIFO_THRESHOLD(kb) \
+@@ -763,10 +763,39 @@
((kb) * 1024 - MVPP2_TX_FIFO_THRESHOLD_MIN)
-+/* RX FIFO threshold in 1KB granularity */
-+#define MVPP23_PORT0_FIFO_TRSH (9 * 1024)
-+#define MVPP23_PORT1_FIFO_TRSH (4 * 1024)
-+#define MVPP23_PORT2_FIFO_TRSH (2 * 1024)
-+
-+/* RX Flow Control Registers */
-+#define MVPP2_RX_FC_REG(port) (0x150 + 4 * (port))
-+#define MVPP2_RX_FC_EN BIT(24)
-+#define MVPP2_RX_FC_TRSH_OFFS 16
-+#define MVPP2_RX_FC_TRSH_MASK (0xFF << MVPP2_RX_FC_TRSH_OFFS)
-+#define MVPP2_RX_FC_TRSH_UNIT 256
-+
/* MSS Flow control */
- #define MSS_FC_COM_REG 0
- #define FLOW_CONTROL_ENABLE_BIT BIT(0)
-@@ -1498,6 +1510,8 @@ struct mvpp2_bm_pool {
-
- void mvpp2_dbgfs_cleanup(struct mvpp2 *priv);
-
-+void mvpp23_rx_fifo_fc_en(struct mvpp2 *priv, int port, bool en);
-+
- #ifdef CONFIG_MVPP2_PTP
- int mvpp22_tai_probe(struct device *dev, struct mvpp2 *priv);
- void mvpp22_tai_tstamp(struct mvpp2_tai *tai, u32 tstamp,
-@@ -1530,4 +1544,5 @@ static inline bool mvpp22_rx_hwtstamping(struct mvpp2_port *port)
- {
- return IS_ENABLED(CONFIG_MVPP2_PTP) && port->rx_hwtstamp;
- }
-+
- #endif
+-#define MSS_SRAM_SIZE 0x800
+-#define FC_QUANTA 0xFFFF
+-#define FC_CLK_DIVIDER 100
++#define MSS_SRAM_SIZE 0x800
++#define MSS_FC_COM_REG 0
++#define FLOW_CONTROL_ENABLE_BIT BIT(0)
++#define FLOW_CONTROL_UPDATE_COMMAND_BIT BIT(31)
++#define FC_QUANTA 0xFFFF
++#define FC_CLK_DIVIDER 100
++
++#define MSS_RXQ_TRESH_BASE 0x200
++#define MSS_RXQ_TRESH_OFFS 4
++#define MSS_RXQ_TRESH_REG(q, fq) (MSS_RXQ_TRESH_BASE + (((q) + (fq)) \
++ * MSS_RXQ_TRESH_OFFS))
++
++#define MSS_RXQ_TRESH_START_MASK 0xFFFF
++#define MSS_RXQ_TRESH_STOP_MASK (0xFFFF << MSS_RXQ_TRESH_STOP_OFFS)
++#define MSS_RXQ_TRESH_STOP_OFFS 16
++
++#define MSS_RXQ_ASS_BASE 0x80
++#define MSS_RXQ_ASS_OFFS 4
++#define MSS_RXQ_ASS_PER_REG 4
++#define MSS_RXQ_ASS_PER_OFFS 8
++#define MSS_RXQ_ASS_PORTID_OFFS 0
++#define MSS_RXQ_ASS_PORTID_MASK 0x3
++#define MSS_RXQ_ASS_HOSTID_OFFS 2
++#define MSS_RXQ_ASS_HOSTID_MASK 0x3F
++
++#define MSS_RXQ_ASS_Q_BASE(q, fq) ((((q) + (fq)) % MSS_RXQ_ASS_PER_REG) \
++ * MSS_RXQ_ASS_PER_OFFS)
++#define MSS_RXQ_ASS_PQ_BASE(q, fq) ((((q) + (fq)) / MSS_RXQ_ASS_PER_REG) \
++ * MSS_RXQ_ASS_OFFS)
++#define MSS_RXQ_ASS_REG(q, fq) (MSS_RXQ_ASS_BASE + MSS_RXQ_ASS_PQ_BASE(q, fq))
++
+ #define MSS_THRESHOLD_STOP 768
++#define MSS_THRESHOLD_START 1024
+
+ /* RX buffer constants */
+ #define MVPP2_SKB_SHINFO_SIZE \
+@@ -1191,6 +1220,9 @@ struct mvpp2_port {
+ bool rx_hwtstamp;
+ enum hwtstamp_tx_types tx_hwtstamp_type;
+ struct mvpp2_hwtstamp_queue tx_hwtstamp_queue[2];
++
++ /* Firmware TX flow control */
++ bool tx_fc;
+ };
+
+ /* The mvpp2_tx_desc and mvpp2_rx_desc structures describe the
diff --git a/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c b/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
-index 3faad04..a472125 100644
+index 4d55344..36e33d5 100644
--- a/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
+++ b/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
-@@ -6536,6 +6536,8 @@ static void mvpp2_mac_link_up(struct phylink_config *config,
- mvpp2_bm_pool_update_fc(port, port->pool_long, tx_pause);
- mvpp2_bm_pool_update_fc(port, port->pool_short, tx_pause);
- }
-+ if (port->priv->hw_version == MVPP23)
-+ mvpp23_rx_fifo_fc_en(port->priv, port->id, tx_pause);
+@@ -742,6 +742,110 @@ static void *mvpp2_buf_alloc(struct mvpp2_port *port,
+ return data;
+ }
+
++/* Routine enable flow control for RXQs condition */
++static void mvpp2_rxq_enable_fc(struct mvpp2_port *port)
++{
++ int val, cm3_state, host_id, q;
++ int fq = port->first_rxq;
++ unsigned long flags;
++
++ spin_lock_irqsave(&port->priv->mss_spinlock, flags);
++
++ /* Remove Flow control enable bit to prevent race between FW and Kernel
++ * If Flow control were enabled, it would be re-enabled.
++ */
++ val = mvpp2_cm3_read(port->priv, MSS_FC_COM_REG);
++ cm3_state = (val & FLOW_CONTROL_ENABLE_BIT);
++ val &= ~FLOW_CONTROL_ENABLE_BIT;
++ mvpp2_cm3_write(port->priv, MSS_FC_COM_REG, val);
++
++ /* Set same Flow control for all RXQs */
++ for (q = 0; q < port->nrxqs; q++) {
++ /* Set stop and start Flow control RXQ thresholds */
++ val = MSS_THRESHOLD_START;
++ val |= (MSS_THRESHOLD_STOP << MSS_RXQ_TRESH_STOP_OFFS);
++ mvpp2_cm3_write(port->priv, MSS_RXQ_TRESH_REG(q, fq), val);
++
++ val = mvpp2_cm3_read(port->priv, MSS_RXQ_ASS_REG(q, fq));
++ /* Set RXQ port ID */
++ val &= ~(MSS_RXQ_ASS_PORTID_MASK << MSS_RXQ_ASS_Q_BASE(q, fq));
++ val |= (port->id << MSS_RXQ_ASS_Q_BASE(q, fq));
++ val &= ~(MSS_RXQ_ASS_HOSTID_MASK << (MSS_RXQ_ASS_Q_BASE(q, fq)
++ + MSS_RXQ_ASS_HOSTID_OFFS));
++
++ /* Calculate RXQ host ID:
++ * In Single queue mode: Host ID equal to Host ID used for
++ * shared RX interrupt
++ * In Multi queue mode: Host ID equal to number of
++ * RXQ ID / number of CoS queues
++ * In Single resource mode: Host ID always equal to 0
++ */
++ if (queue_mode == MVPP2_QDIST_SINGLE_MODE)
++ host_id = port->nqvecs;
++ else if (queue_mode == MVPP2_QDIST_MULTI_MODE)
++ host_id = q;
++ else
++ host_id = 0;
++
++ /* Set RXQ host ID */
++ val |= (host_id << (MSS_RXQ_ASS_Q_BASE(q, fq)
++ + MSS_RXQ_ASS_HOSTID_OFFS));
++
++ mvpp2_cm3_write(port->priv, MSS_RXQ_ASS_REG(q, fq), val);
++ }
++
++ /* Notify Firmware that Flow control config space ready for update */
++ val = mvpp2_cm3_read(port->priv, MSS_FC_COM_REG);
++ val |= FLOW_CONTROL_UPDATE_COMMAND_BIT;
++ val |= cm3_state;
++ mvpp2_cm3_write(port->priv, MSS_FC_COM_REG, val);
++
++ spin_unlock_irqrestore(&port->priv->mss_spinlock, flags);
++}
++
++/* Routine disable flow control for RXQs condition */
++static void mvpp2_rxq_disable_fc(struct mvpp2_port *port)
++{
++ int val, cm3_state, q;
++ unsigned long flags;
++ int fq = port->first_rxq;
++
++ spin_lock_irqsave(&port->priv->mss_spinlock, flags);
++
++ /* Remove Flow control enable bit to prevent race between FW and Kernel
++ * If Flow control were enabled, it would be re-enabled.
++ */
++ val = mvpp2_cm3_read(port->priv, MSS_FC_COM_REG);
++ cm3_state = (val & FLOW_CONTROL_ENABLE_BIT);
++ val &= ~FLOW_CONTROL_ENABLE_BIT;
++ mvpp2_cm3_write(port->priv, MSS_FC_COM_REG, val);
++
++ /* Disable Flow control for all RXQs */
++ for (q = 0; q < port->nrxqs; q++) {
++ /* Set threshold 0 to disable Flow control */
++ val = 0;
++ val |= (0 << MSS_RXQ_TRESH_STOP_OFFS);
++ mvpp2_cm3_write(port->priv, MSS_RXQ_TRESH_REG(q, fq), val);
++
++ val = mvpp2_cm3_read(port->priv, MSS_RXQ_ASS_REG(q, fq));
++
++ val &= ~(MSS_RXQ_ASS_PORTID_MASK << MSS_RXQ_ASS_Q_BASE(q, fq));
++
++ val &= ~(MSS_RXQ_ASS_HOSTID_MASK << (MSS_RXQ_ASS_Q_BASE(q, fq)
++ + MSS_RXQ_ASS_HOSTID_OFFS));
++
++ mvpp2_cm3_write(port->priv, MSS_RXQ_ASS_REG(q, fq), val);
++ }
++
++ /* Notify Firmware that Flow control config space ready for update */
++ val = mvpp2_cm3_read(port->priv, MSS_FC_COM_REG);
++ val |= FLOW_CONTROL_UPDATE_COMMAND_BIT;
++ val |= cm3_state;
++ mvpp2_cm3_write(port->priv, MSS_FC_COM_REG, val);
++
++ spin_unlock_irqrestore(&port->priv->mss_spinlock, flags);
++}
++
+ /* Release buffer to BM */
+ static inline void mvpp2_bm_pool_put(struct mvpp2_port *port, int pool,
+ dma_addr_t buf_dma_addr,
+@@ -3008,6 +3112,9 @@ static void mvpp2_cleanup_rxqs(struct mvpp2_port *port)
+
+ for (queue = 0; queue < port->nrxqs; queue++)
+ mvpp2_rxq_deinit(port, port->rxqs[queue]);
++
++ if (port->tx_fc)
++ mvpp2_rxq_disable_fc(port);
+ }
+
+ /* Init all Rx queues for port */
+@@ -3020,6 +3127,10 @@ static int mvpp2_setup_rxqs(struct mvpp2_port *port)
+ if (err)
+ goto err_cleanup;
}
-
- mvpp2_port_enable(port);
-@@ -7004,6 +7006,55 @@ static void mvpp22_rx_fifo_init(struct mvpp2 *priv)
- mvpp2_write(priv, MVPP2_RX_FIFO_INIT_REG, 0x1);
- }
-
-+/* Configure Rx FIFO Flow control thresholds */
-+static void mvpp23_rx_fifo_fc_set_tresh(struct mvpp2 *priv)
-+{
-+ int port, val;
-+
-+ /* Port 0: maximum speed -10Gb/s port
-+ * required by spec RX FIFO threshold 9KB
-+ * Port 1: maximum speed -5Gb/s port
-+ * required by spec RX FIFO threshold 4KB
-+ * Port 2: maximum speed -1Gb/s port
-+ * required by spec RX FIFO threshold 2KB
-+ */
-+
-+ /* Without loopback port */
-+ for (port = 0; port < (MVPP2_MAX_PORTS - 1); port++) {
-+ if (port == 0) {
-+ val = (MVPP23_PORT0_FIFO_TRSH / MVPP2_RX_FC_TRSH_UNIT)
-+ << MVPP2_RX_FC_TRSH_OFFS;
-+ val &= MVPP2_RX_FC_TRSH_MASK;
-+ mvpp2_write(priv, MVPP2_RX_FC_REG(port), val);
-+ } else if (port == 1) {
-+ val = (MVPP23_PORT1_FIFO_TRSH / MVPP2_RX_FC_TRSH_UNIT)
-+ << MVPP2_RX_FC_TRSH_OFFS;
-+ val &= MVPP2_RX_FC_TRSH_MASK;
-+ mvpp2_write(priv, MVPP2_RX_FC_REG(port), val);
-+ } else {
-+ val = (MVPP23_PORT2_FIFO_TRSH / MVPP2_RX_FC_TRSH_UNIT)
-+ << MVPP2_RX_FC_TRSH_OFFS;
-+ val &= MVPP2_RX_FC_TRSH_MASK;
-+ mvpp2_write(priv, MVPP2_RX_FC_REG(port), val);
-+ }
-+ }
-+}
-+
-+/* Configure Rx FIFO Flow control thresholds */
-+void mvpp23_rx_fifo_fc_en(struct mvpp2 *priv, int port, bool en)
-+{
-+ int val;
-+
-+ val = mvpp2_read(priv, MVPP2_RX_FC_REG(port));
-+
-+ if (en)
-+ val |= MVPP2_RX_FC_EN;
-+ else
-+ val &= ~MVPP2_RX_FC_EN;
-+
-+ mvpp2_write(priv, MVPP2_RX_FC_REG(port), val);
-+}
-+
- static void mvpp22_tx_fifo_set_hw(struct mvpp2 *priv, int port, int size)
- {
- int threshold = MVPP2_TX_FIFO_THRESHOLD(size);
-@@ -7155,6 +7206,8 @@ static int mvpp2_init(struct platform_device *pdev, struct mvpp2 *priv)
- } else {
- mvpp22_rx_fifo_init(priv);
- mvpp22_tx_fifo_init(priv);
-+ if (priv->hw_version == MVPP23)
-+ mvpp23_rx_fifo_fc_set_tresh(priv);
- }
-
- if (priv->hw_version == MVPP21)
++
++ if (port->tx_fc)
++ mvpp2_rxq_enable_fc(port);
++
+ return 0;
+
+ err_cleanup:
--
1.9.1