--- v9
+++ v4
@@ -1,121 +1,79 @@
From: Stefan Chulski <stefanc@marvell.com>
-The PP2v23 hardware supports a feature allowing to double the
-size of BPPI by decreasing number of pools from 16 to 8.
-Increasing of BPPI size protect BM drop from BPPI underrun.
-Underrun could occurred due to stress on DDR and as result slow buffer
-transition from BPPE to BPPI.
-New BPPI threshold recommended by spec is:
-BPPI low threshold - 640 buffers
-BPPI high threshold - 832 buffers
-Supported only in PPv23.
+This patch enables global flow control in FW and in the phylink validate mask.
Signed-off-by: Stefan Chulski <stefanc@marvell.com>
---
- drivers/net/ethernet/marvell/mvpp2/mvpp2.h | 8 +++++
- drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c | 35 +++++++++++++++++++-
- 2 files changed, 42 insertions(+), 1 deletion(-)
+ drivers/net/ethernet/marvell/mvpp2/mvpp2.h | 3 +++
+ drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c | 20 +++++++++++++++++++-
+ 2 files changed, 22 insertions(+), 1 deletion(-)
diff --git a/drivers/net/ethernet/marvell/mvpp2/mvpp2.h b/drivers/net/ethernet/marvell/mvpp2/mvpp2.h
-index 0731dc7..9b525b60 100644
+index f34e260..e9625fb 100644
--- a/drivers/net/ethernet/marvell/mvpp2/mvpp2.h
+++ b/drivers/net/ethernet/marvell/mvpp2/mvpp2.h
-@@ -324,6 +324,10 @@
- #define MVPP2_BM_HIGH_THRESH_MASK 0x7f0000
- #define MVPP2_BM_HIGH_THRESH_VALUE(val) ((val) << \
- MVPP2_BM_HIGH_THRESH_OFFS)
-+#define MVPP2_BM_BPPI_HIGH_THRESH 0x1E
-+#define MVPP2_BM_BPPI_LOW_THRESH 0x1C
-+#define MVPP23_BM_BPPI_HIGH_THRESH 0x34
-+#define MVPP23_BM_BPPI_LOW_THRESH 0x28
- #define MVPP2_BM_INTR_CAUSE_REG(pool) (0x6240 + ((pool) * 4))
- #define MVPP2_BM_RELEASED_DELAY_MASK BIT(0)
- #define MVPP2_BM_ALLOC_FAILED_MASK BIT(1)
-@@ -352,6 +356,10 @@
- #define MVPP2_OVERRUN_ETH_DROP 0x7000
- #define MVPP2_CLS_ETH_DROP 0x7020
+@@ -1022,6 +1022,9 @@ struct mvpp2 {
+ /* CM3 SRAM pool */
+ struct gen_pool *sram_pool;
-+#define MVPP22_BM_POOL_BASE_ADDR_HIGH_REG 0x6310
-+#define MVPP22_BM_POOL_BASE_ADDR_HIGH_MASK 0xff
-+#define MVPP23_BM_8POOL_MODE BIT(8)
++ /* Global TX Flow Control config */
++ bool global_tx_fc;
+
- /* Hit counters registers */
- #define MVPP2_CTRS_IDX 0x7040
- #define MVPP22_CTRS_TX_CTR(port, txq) ((txq) | ((port) << 3) | BIT(7))
+ bool custom_dma_mask;
+
+ /* Spinlocks for CM3 shared memory configuration */
diff --git a/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c b/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
-index 90c9265..3faad04 100644
+index 64534f0..4d55344 100644
--- a/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
+++ b/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
-@@ -69,6 +69,11 @@ enum mvpp2_bm_pool_log_num {
- module_param(queue_mode, int, 0444);
- MODULE_PARM_DESC(queue_mode, "Set queue_mode (single=0, multi=1)");
+@@ -5963,6 +5963,11 @@ static void mvpp2_phylink_validate(struct phylink_config *config,
+ phylink_set(mask, Autoneg);
+ phylink_set_port_modes(mask);
-+static int bm_underrun_protect = 1;
-+
-+module_param(bm_underrun_protect, int, 0444);
-+MODULE_PARM_DESC(bm_underrun_protect, "Set BM underrun protect feature (0-1), def=1");
-+
- /* Utility/helper methods */
-
- void mvpp2_write(struct mvpp2 *priv, u32 offset, u32 data)
-@@ -423,6 +428,21 @@ static int mvpp2_bm_pool_create(struct device *dev, struct mvpp2 *priv,
-
- val = mvpp2_read(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id));
- val |= MVPP2_BM_START_MASK;
-+
-+ val &= ~MVPP2_BM_LOW_THRESH_MASK;
-+ val &= ~MVPP2_BM_HIGH_THRESH_MASK;
-+
-+ /* Set 8 Pools BPPI threshold if BM underrun protection feature
-+ * was enabled
-+ */
-+ if (priv->hw_version == MVPP23 && bm_underrun_protect) {
-+ val |= MVPP2_BM_LOW_THRESH_VALUE(MVPP23_BM_BPPI_LOW_THRESH);
-+ val |= MVPP2_BM_HIGH_THRESH_VALUE(MVPP23_BM_BPPI_HIGH_THRESH);
-+ } else {
-+ val |= MVPP2_BM_LOW_THRESH_VALUE(MVPP2_BM_BPPI_LOW_THRESH);
-+ val |= MVPP2_BM_HIGH_THRESH_VALUE(MVPP2_BM_BPPI_HIGH_THRESH);
++ if (port->priv->global_tx_fc) {
++ phylink_set(mask, Pause);
++ phylink_set(mask, Asym_Pause);
+ }
+
- mvpp2_write(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id), val);
+ switch (state->interface) {
+ case PHY_INTERFACE_MODE_10GBASER:
+ case PHY_INTERFACE_MODE_XAUI:
+@@ -6981,7 +6986,7 @@ static int mvpp2_probe(struct platform_device *pdev)
+ struct resource *res;
+ void __iomem *base;
+ int i, shared;
+- int err;
++ int err, val;
- bm_pool->size = size;
-@@ -591,6 +611,16 @@ static int mvpp2_bm_pools_init(struct device *dev, struct mvpp2 *priv)
- return err;
- }
-
-+/* Routine enable PPv23 8 pool mode */
-+static void mvpp23_bm_set_8pool_mode(struct mvpp2 *priv)
-+{
-+ int val;
+ priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
+ if (!priv)
+@@ -7035,6 +7040,10 @@ static int mvpp2_probe(struct platform_device *pdev)
+ return err;
+ else if (err)
+ dev_warn(&pdev->dev, "Fail to alloc CM3 SRAM\n");
+
-+ val = mvpp2_read(priv, MVPP22_BM_POOL_BASE_ADDR_HIGH_REG);
-+ val |= MVPP23_BM_8POOL_MODE;
-+ mvpp2_write(priv, MVPP22_BM_POOL_BASE_ADDR_HIGH_REG, val);
-+}
-+
- static int mvpp2_bm_init(struct device *dev, struct mvpp2 *priv)
- {
- enum dma_data_direction dma_dir = DMA_FROM_DEVICE;
-@@ -644,6 +674,9 @@ static int mvpp2_bm_init(struct device *dev, struct mvpp2 *priv)
- if (!priv->bm_pools)
- return -ENOMEM;
-
-+ if (priv->hw_version == MVPP23 && bm_underrun_protect)
-+ mvpp23_bm_set_8pool_mode(priv);
-+
- err = mvpp2_bm_pools_init(dev, priv);
- if (err < 0)
- return err;
-@@ -6490,7 +6523,7 @@ static void mvpp2_mac_link_up(struct phylink_config *config,
- val);
++ /* Enable global Flow Control only if handler to SRAM not NULL */
++ if (priv->cm3_base)
++ priv->global_tx_fc = true;
}
-- if (port->priv->global_tx_fc) {
-+ if (port->priv->global_tx_fc && bm_underrun_protect) {
- port->tx_fc = tx_pause;
- if (tx_pause)
- mvpp2_rxq_enable_fc(port);
+ if (priv->hw_version != MVPP21 && dev_of_node(&pdev->dev)) {
+@@ -7205,6 +7214,15 @@ static int mvpp2_probe(struct platform_device *pdev)
+ goto err_port_probe;
+ }
+
++ /* Enable global flow control. In this stage global
++ * flow control enabled, but still disabled per port.
++ */
++ if (priv->global_tx_fc && priv->hw_version != MVPP21) {
++ val = mvpp2_cm3_read(priv, MSS_FC_COM_REG);
++ val |= FLOW_CONTROL_ENABLE_BIT;
++ mvpp2_cm3_write(priv, MSS_FC_COM_REG, val);
++ }
++
+ mvpp2_dbgfs_init(priv, pdev->name);
+
+ platform_set_drvdata(pdev, priv);
--
1.9.1